PCF8536AT datasheet(51/103 Pages) NXP

51 / 103 page

PCA8530

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Product data sheet

Rev. 2 — 25 September 2014

51 of 103

NXP Semiconductors

PCA8530

Automotive 102 x 4 Chip-On-Glass LCD segment driver

8.14 Display RAM

The display RAM is a static 102

 4-bit RAM which stores LCD data. Logic 1 in the RAM

bit map indicates the on-state, logic 0 the off-state of the corresponding LCD element.

There is a one-to-one correspondence between

• the bits in the RAM bitmap and the LCD segments/elements

• the RAM columns and the segment outputs

• the RAM rows and the backplane outputs.

The display RAM bit map, Figure 29 on page 53, shows row 0 to row 3 which correspond

with the backplane outputs COM0 to COM3, and column 0 to column 101 which

correspond with the segment outputs S0 to S101. In multiplexed LCD applications, the

data of each row of the display RAM is time-multiplexed with the corresponding backplane

(row 0 with COM0, row 1 with COM1, and so on).

When display data is transmitted to the PCA8530, the display bytes received are stored in

the display RAM in accordance with the selected LCD multiplex drive mode. The data is

stored as it arrives and does not wait for the acknowledge cycle as with the commands.

Depending on the current multiplex drive mode, data is stored singularly, in pairs, or

quadruples.

8.14.1 Data pointer

The addressing mechanism for the display RAM is realized using a data pointer. This

allows the loading of an individual display data byte, or a series of display data bytes into

any location of the display RAM. The sequence commences with the initialization of the

data pointer by the Data-pointer-init command followed by setting the data pointer with the

Data-pointer-MSB and Data-pointer-LSB commands. Then the display RAM content can

be written. An arriving data byte is stored starting at the display RAM address indicated by

the data pointer.

The data pointer is automatically incremented in accordance with the chosen LCD

multiplex drive mode configuration. After each byte is stored, the content of the data

pointer is incremented

• by eight (static drive mode)

• by four (1:2 multiplex drive mode)

• by two (1:4 multiplex drive mode)

When the address counter reaches the end of the RAM, it stops incrementing after the last

byte is transmitted. Redundant bits of the last byte and subsequent bytes transmitted are

discarded. To send new RAM data, the data pointer must be reset.

If a data access with the I2C- or SPI-bus is terminated early, then the state of the data

pointer is unknown. The data pointer must then be rewritten before further RAM accesses.

8.14.1.1

Data pointer in cascade configuration

In cascaded applications each PCA8530 in the cascade must be addressed separately.

Initially, the first PCA8530 is selected by sending the Device-address command matching

the first hardware address. Then the data pointer is set to the preferred display RAM

address with the Data-pointer commands.

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