PCF8536AT datasheet(53/103 Pages) NXP

53 / 103 page

PCA8530

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Product data sheet

Rev. 2 — 25 September 2014

53 of 103

NXP Semiconductors

PCA8530

Automotive 102 x 4 Chip-On-Glass LCD segment driver

8.14.2.3

RAM filling in 1:4 multiplex drive mode

In the 1:4 multiplex drive mode the eight transmitted data bits are placed in two

successive display RAM columns of four rows (see Table 41).

In order to fill the whole four RAM rows 51 bytes need to be sent to the PCA8530.

Depending on the start address of the data pointer, there is the possibility for a boundary

condition. This occurs when more data bits are sent than fit into the remaining RAM. The

additional data bits are discarded.

8.14.3 Bank selection

The PCA8530 includes a RAM bank switching feature in the static and 1:2 multiplex drive

modes. A bank can be thought of as a RAM row or a collection of RAM rows. The RAM

bank switching gives the provision for preparing display information in an alternative bank

and to be able to switch to it once it is complete. Figure 29 shows the location of the banks

relative to the RAM map.

Input and output banks can be set independently from one another with the bank-select

commands (see Section 8.7.2 on page 24). Figure 31 shows the concept.

Table 41.

RAM filling in 1:4 multiplex drive mode

RAM row/

backplane

output

(COM)

RAM column/Segment output (S)

100

101

aa7

aa3

ab7

ab3

bx3

by7

by3

aa6

aa2

ab6

ab2

bx2

by6

by2

aa5

aa1

ab5

ab1

bx1

by5

by1

aa4

aa0

ab4

ab0

bx0

by4

by0

The display RAM bitmap shows the direct relationship between the display RAM column and the

segment outputs, between the bits in a RAM row and the backplane outputs, and between the

RAM rows and banks.

Fig 29. Display RAM bitmap and bank definition

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