PCF8536AT datasheet(57/103 Pages) NXP

57 / 103 page

PCA8530

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 25 September 2014

57 of 103

NXP Semiconductors

PCA8530

Automotive 102 x 4 Chip-On-Glass LCD segment driver

9.2 I2C interface

The I2C-bus is selected by connecting pin IFS to VDD1.

The I2C-bus is for bidirectional, two-line communication between different ICs or modules.

The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must

be connected to a positive supply via a pull-up resistor when connected to the output

stages of a device. Data transfer may be initiated only when the bus is not busy.

In Chip-On-Glass (COG) applications, where the track resistance between the SDA

output pin to the system SDA input line can be significant, the bus pull-up resistor and the

Indium Tin Oxide (ITO) track resistance may generate a voltage divider. As a

consequence it may be possible that the acknowledge cycle, generated by the LCD driver,

cannot be interpreted as logic 0 by the master. Therefore it is an advantage for COG

applications to have the acknowledge output separated from the data line. For that

reason, the SDA line of the PCA8530 is split into SDI/SDAIN and SDAOUT.

In COG applications where the acknowledge cycle is required, it is necessary to minimize

the track resistance from the SDAOUT pin to the system SDI/SDAIN line to guarantee a

valid LOW level.

By splitting the SDA line into SDI/SDAIN and SDAOUT (having the SDAOUT open

circuit), the device could be used in a mode that ignores the acknowledge cycle.

Separating the acknowledge output from the serial data line can avoid design efforts to

generate a valid acknowledge level. However, in that case the I2C-bus master has to be

set up in such a way that it ignores the acknowledge cycle.2

By connecting pin SDAOUT to pin SDI/SDAIN, the SDI/SDAIN line becomes fully I2C-bus

compatible. The following definition assumes SDI/SDAIN and SDAOUT are connected

and refers to the pair as SDA.

9.2.1 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain

stable during the HIGH period of the clock pulse as changes in the data line at this time

are interpreted as a control signal (see Figure 33).

9.2.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy.

A HIGH-to-LOW change of the data line, while the clock is HIGH is defined as the START

condition (S).

For further information, consider the NXP application note: Ref. 1 “AN10170”.

Fig 33. I2C-bus - bit transfer

PCF8536AT 数据表(PDF) 57 Page - NXP Semiconductors

PCF8536AT 数据表(HTML) 57 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载