PCF8536AT datasheet(101/103 Pages) NXP

101 / 103 page

PCA8530

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 25 September 2014

101 of 103

NXP Semiconductors

PCA8530

Automotive 102 x 4 Chip-On-Glass LCD segment driver

27. Figures

Fig 1.

Block diagram of PCA8530 . . . . . . . . . . . . . . . . . .4

Fig 2.

Pinning diagram of PCA8530DUG. . . . . . . . . . . . .5

Fig 3.

Recommended start-up sequence when using the

internal charge pump and the internal

clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Fig 4.

Recommended start-up sequence when using an

external supplied VLCD and the internal

clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Fig 5.

Recommended start-up sequence when using the

internal charge pump and an external

clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Fig 6.

Recommended start-up sequence when using an

external supplied VLCD and an external

clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Fig 7.

Recommended power-down sequence for minimum

power-down current when using the internal

charge pump and the internal clock signal. . . . . .29

Fig 8.

Recommended power-down sequence when using

an external supplied VLCD and the internal

clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Fig 9.

Recommended power-down sequence when using

the internal charge pump and an external

clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Fig 10. Recommended power-down sequence when using

an external supplied VLCD and an external

clock signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Fig 11. Example of display types suitable for PCA8530 .32

Fig 12. Typical system configuration if using the internal

VLCD generation and I2C-bus . . . . . . . . . . . . . . . .33

Fig 13. Typical system configuration if using the

external VLCD and SPI-bus . . . . . . . . . . . . . . . . .33

Fig 14. VLCD generation including temperature

compensation . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Fig 15. VLCD programming of PCA8530 (assuming

VT[8:0] = 0h) . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Fig 16. Charge pump model (used to characterize

the driving strength) . . . . . . . . . . . . . . . . . . . . . . .36

Fig 17. Charge pump driving capability with

VDD2 = 3.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Fig 18. Charge pump driving capability with

VDD2 = 5.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Fig 19. VLCD with respect to Iload at VDD2 = 3 V . . . . . . . .39

Fig 20. VLCD with respect to Iload at VDD2 = 5 V . . . . . . . .39

Fig 21. Temperature measurement block with digital

temperature filter . . . . . . . . . . . . . . . . . . . . . . . . .40

Fig 22. Temperature measurement delay . . . . . . . . . . . .41

Fig 23. Example of segmented temperature coefficients.42

Fig 24. Electro-optical characteristic: relative transmission

curve of the liquid. . . . . . . . . . . . . . . . . . . . . . . . .45

Fig 25. Static drive mode waveforms, line inversion mode

(n = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Fig 26. Waveforms for the 1:2 multiplex drive mode,

1⁄2 bias, line inversion mode (n = 1) . . . . . . . . . . .47

Fig 27. Waveforms for the 1:2 multiplex drive mode,

1⁄3 bias, line inversion mode (n = 1) . . . . . . . . . . .48

Fig 28. Waveforms for the 1:4 multiplex drive mode,

1⁄3 bias, line inversion mode (n = 1). . . . . . . . . . . 49

Fig 29. Display RAM bitmap and bank definition . . . . . . 53

Fig 30. Bank selection in multiplex drive mode 1:2 . . . . . 54

Fig 31. Example of the Bank-select command with

multiplex drive mode 1:2 . . . . . . . . . . . . . . . . . . . 54

Fig 32. Control byte format . . . . . . . . . . . . . . . . . . . . . . . 56

Fig 33. I2C-bus - bit transfer . . . . . . . . . . . . . . . . . . . . . . 57

Fig 34. I2C-bus - definition of START and STOP

conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Fig 35. I2C-bus - system configuration . . . . . . . . . . . . . . 58

Fig 36. Acknowledgement on the I2C-bus. . . . . . . . . . . . 59

Fig 37. I2C-bus protocol - write mode . . . . . . . . . . . . . . . 60

Fig 38. I2C-bus protocol - read mode . . . . . . . . . . . . . . . 60

Fig 39. SPI-bus protocol - data transfer overview . . . . . . 61

Fig 40. SPI-bus example. . . . . . . . . . . . . . . . . . . . . . . . . 62

Fig 41. SPI-bus protocol - read example. . . . . . . . . . . . . 62

Fig 42. SPI-bus protocol - write example . . . . . . . . . . . . 62

Fig 43. Device protection diagram . . . . . . . . . . . . . . . . . 63

Fig 44. Typical IDD1 with respect to temperature . . . . . . . 69

Fig 45. Typical IDD2 with respect to temperature . . . . . . . 69

Fig 46. Typical IDD3 with respect to temperature . . . . . . . 70

Fig 47. Typical IDD(LCD) with respect to temperature . . . . 70

Fig 48. Typical VLCD variation with respect to

temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Fig 49. Typical frame frequency variation with respect to

temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Fig 50. Measurement temperature variation with

respect to temperature . . . . . . . . . . . . . . . . . . . . 72

Fig 51. Driver timing waveforms . . . . . . . . . . . . . . . . . . . 73

Fig 52. I2C-bus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Fig 53. SPI-bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Fig 54. Recommended ITO connections for the I2C

interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Fig 55. Recommended ITO connections for the SPI

interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Fig 56. Cascaded configuration with two PCA8530

with external VLCD and internal clock . . . . . . . . . 81

Fig 57. Cascaded configuration with two PCA8530

with internal VLCD and external clock . . . . . . . . . 82

Fig 58. Cascade configuration for data reading . . . . . . . 84

Fig 59. Bare die outline of PCA8530DUG . . . . . . . . . . . . 85

Fig 60. Alignment marks . . . . . . . . . . . . . . . . . . . . . . . . . 89

Fig 61. Tray details of PCA8530DUG . . . . . . . . . . . . . . . 91

Fig 62. Die alignment in the tray . . . . . . . . . . . . . . . . . . . 92

PCF8536AT 数据表(PDF) 101 Page - NXP Semiconductors

PCF8536AT 数据表(HTML) 101 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载