LTM4686BEVPBF datasheet(28/130 Pages) AD

28 / 130 page

LTM4686B

Rev. 0

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OPERATION

(MFR_IOUT_CAL_GAIN_TCn) (uncommon to alter this

parameter from its NVM-Factory default setting).

Altering the gain or offset of the power stage sen-

sors (MFR_TEMP_1_GAINn and MFR_TEMP_1_

OFFSETn)—or that of the external temperature sensor,

when an external temperature sensor is used on the

TSNS1a pin. (Uncommon to alter this parameter from

its NVM-factory default setting).

Configuring whether the LTM4686B Pulls SHARE_CLK

logic low when SVIN has fallen outside Its UVLO thresh-

olds (MFR_PWM_CONFIG[4]). MFR_PWM_CONFIG

cannot be changed on the fly; switching action must be

off (uncommon to alter this parameter from its NVM-

factory default setting).

Configuring whether the LTM4686B’s output voltage

digital servos are active vs disengaged (MFR_PWM_

MODEn[6]. Uncommon to alter this parameter from its

NVM-factory default settings).

Configuring whether the LTM4686B’s current limit

range is set to high range vs low range. (MFR_PWM_

MODEn[7]. Not recommended to alter this parameter

from its NVM-factory default settings).

Remaining LTM4686B status that can be queried over I2C

communications follow:

Access to three “hand-shaking” status bits (MFR_

COMMON[6:4]) to ease implementation of PMBus

busy protocols, i.e., enabling fast and robust system

level communication through polling of these bits to

infer LTM4686B’s readiness to act on subsequent I2C

writes. (See PMBus communication and command

processing, in the Applications Information section.)

Providing a means to determine whether the LTM4686B

NVM download to RAM has occurred (“NVM Initialized,”

MFR_COMMON[3]).

Providing a means other than ARA protocol to deter-

mine whether the LTM4686B is pulling ALERT low

(MFR_COMMON[7]).

Detecting a SHARE_CLK timeout event

(MFR_COMMON[1]).

Verifying or Altering the Slave Address of the LTM4686B

(MFR_ADDRESS).

POWER MODULE OVERVIEW

A dedicated remote-sense amplifier precisely kelvin-

senses VOUT0’s load via the differential pin-pair formed

by VOSNS0+ and VOSNS0–. VOUT0 can be commanded to

between 0.5VDC and 3.6VDC. VOUT1 is sensed via the pin-

pair formed by VOSNS1 and signal ground of the module’s

SGND. VOUT1 can be commanded to between 0.5VDC and

3.6VDC. Output voltage readback telemetry is available

over I2C (READ_VOUTn registers). Peak output voltage

readback telemetry is accessible in the MFR_READ_

VOUT_PEAKn registers. If VOSNS0– exceeds VOSNS0+, no

phase reversal of the differentially-sensed output voltage

feedback signal occurs (Note 12). Similarly, no phase

reversal occurs when SGND exceeds VOSNS1(Note 12).

For added flexibility, the VOSNSO+/VOSNSO– feedback pins

can be configured as the control loop feedback path for

both VOUT0 and VOUT1 by setting MFR_PWM_CONFIG[7] =

1b. (See Figure 35).

The typical application schematic is shown in Figure 62

on the back page of this data sheet.

The LTM4686B can operate from input voltages between

4.5V and 5.75V (see Figure 62). Internal LDOs—3.3V

(VDD33), derived from INTVCC, and 2.5V (VDD25), derived

from VDD33—bias the LTM4686B’s digital circuitry. Control

IC bias (SVIN) is routed independent of the inputs to the

power stages (VIN0, VIN1); this enables step-down DC/DC

conversion from less than 4.5V input (see Figure 31), so

long as auxiliary power (~ 5V) is available to bias SVIN

and INTVCC (the module’s control IC) appropriately. (See

also Test Circuit 2). Furthermore, the inputs of the two

LTM4686BEVPBF 数据表(PDF) 28 Page - Analog Devices

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