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LTM4686BEVPBF 数据表(PDF) 13 Page - Analog Devices |
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LTM4686BEVPBF 数据表(HTML) 13 Page - Analog Devices |
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13 / 130 page  PACKAGE ROW AND COLUMN LABELING MAY VARY AMONG µModule PRODUCTS. REVIEW EACH PACKAGE LAYOUT CAREFULLY. LTM4686B 13 Rev. 0 For more information www.analog.com TYPICAL PERFORMANCE CHARACTERISTICS READ_IOUT of 25 LTM4686Bs (DC3089) 5VIN, 1VOUT READ_IOUT of 25 LTM4686Bs (DC3089) 5VIN, 1VOUT READ_IOUT of 25 LTM4686Bs (DC3089) 5VIN, 1VOUT READ_IOUT CHANNEL READBACK (A) 4686B G19 0 3 6 9 12 15 TJ = 125°C, IOUTn = 10A, SYSTEM HAVING REACHED THERMALLY STEADY-STATE CONDITION, NO AIRFLOW PIN FUNCTIONS VOUT0 (A1, B1, C1, D1): Channel 0 Output Voltage. GND (A2–A8, B2–B7, C2, C4–C8, D2, D5, E1, E9, F1, F8, G1, G8–G9, H1, H8–H9, J2, J8, K2, K5–K8, L2–L7, M2– M8): Power Ground of the LTM4686B. Power return for VOUT0 and VOUT1. VIN0 (A9, B9, C9, D9): Positive Power Input to Channel 0 Switching Stage. Provide sufficient decoupling capaci- tance in the form of multilayer ceramic capacitors (MLCCs) and low ESR electrolytic (or equivalent) to handle reflected input current ripple from the step-down switching stage. MLCCs should be placed as close to the LTM4686B as physically possible. See Layout Recommendations in the Applications Information section. SW0 (B8): Switching Node of Channel 0 Step-Down Converter Stage. Used for test purposes or EMI-snubbing. May be routed a short distance to a local test point to monitor switching action of Channel 0, if desired, but do not route near any sensitive signals; otherwise, leave elec- trically isolated (open). TSNS0 (C3 and D3): Temperature Sensor Node for Channel 0. Pads C3 and D3 are connected to each other internal to the module. It is permissible to leave these pads electrically open circuit and to only solder these pins to mounting pads on the PC board for mechanical integrity purposes. However, it is acceptable to electrically connect C3 to D3 on the PC board. SDA (D4): Serial Bus Data Open-Drain Input and Output. A pull-up resistor to 3.3V is required in the application. COMP0b, COMP1b (D6 and J6, Respectively): Internal Loop Compensation Networks for Channels 0 and 1, Respectively. For the vast majority of applications, the internal, default loop compensation of the LTM4686B is suitable to apply “as is”, and yields very satisfactory results: apply the default loop compensation to the control loops of Channels 0 and 1 by simply connecting COMP0a to COMP0b and COMP1a to COMP1b, respectively. In contrast, when more specialized applications require a personal touch the optimization of control loop response, READ_IOUT CHANNEL READBACK (A) 4686B G17 0 3 6 9 12 15 TJ = –40°C, IOUTn = 10A, SYSTEM HAVING REACHED THERMALLY STEADY-STATE CONDITION, NO AIRFLOW READ_IOUT CHANNEL READBACK (A) 4686B G18 0 3 6 9 12 15 TJ = 25°C, IOUTn = 10A, SYSTEM HAVING REACHED THERMALLY STEADY-STATE CONDITION, NO AIRFLOW TA = 25°C, 5VIN to 1VOUT, switching frequency set per Table 7, unless otherwise noted. |
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