LTM4686BEVPBF datasheet(10/130 Pages) AD

10 / 130 page

LTM4686B

Rev. 0

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ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listing under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating conditions for extended periods may affect device

reliability and lifetime.

Note 2: The LTM4686B is tested under pulsed-load conditions such

that TJ ≈ TA. The LTM4686BE is guaranteed to meet performance

specifications over the 0°C to 125°C internal operating temperature range.

Specifications over the –40°C to 125°C internal operating temperature

range are assured by design, characterization and correlation with

statistical process controls. The LTM4686BI is guaranteed to meet

specifications over the full –40°C to 125°C internal operating temperature

range. Note that the maximum ambient temperature consistent with

these specifications is determined by specific operating conditions in

conjunction with board layout, the rated package thermal resistance and

other environmental factors.

Note 3: The LTM4686B’s EEPROM temperature range for valid write

commands is 0°C to 85°C. To achieve guaranteed EEPROM data retention,

execution of the “STORE_USER_ALL” command—i.e., uploading RAM

contents to NVM—outside this temperature range is not recommended.

However, as long as the LTM4686B’s EEPROM temperature is less than

130°C, the LTM4686B will obey the STORE_USER_ALL command.

Only when EEPROM temperature exceeds 130°C, the LTM4686B

will not act on any STORE_USER_ALL transactions: instead, the

LTM4686B NACKs the serial command and asserts its relevant CML

(communications, memory, logic) fault bits. EEPROM temperature can be

queried prior to commanding STORE_USER_ALL; see the Applications

Information section.

Note 4: The two power inputs—VIN0 and VIN1—and their respective power

outputs—VOUT0 and VOUT1—are tested independently in production. A

shorthand notation is used in this document that allows these parameters

to be referred to by “VINn” and “VOUTn”, where n is permitted to take on a

value of 0 or 1. This italicized “n” notation and convention is extended to

encompass all such pin names, as well as register names with channel-

specific, i.e., paged data. For example, VOUT_COMMANDn refers to the

VOUT_COMMAND command code data located in Pages 0 and 1, which

in turn relate to Channels 0 (VOUT0) and Channel 1 (VOUT1). Registers

containing non-page-specific data, i.e., whose data is “global” to the

module or applies to both of the module’s Channels lack the italicized “n”,

e.g., FREQUENCY_SWITCH.

Note 5: VOUTn(DC) and line and load regulation tests are performed in

production with digital servo disengaged (MFR_PWM_MODEn[6] = 0b)

and low VOUTn range selected (MFR_PWM_MODEn[1]) = 1b.

The digital servo control loop is exercised in production (setting

MFR_ PWM_MODEn[6] = 1b), but convergence of the output voltage

to its final settling value is not necessarily observed in final test—due

to potentially long time constants involved—and is instead guaranteed

by the output voltage readback accuracy specification. Evaluation

in application demonstrates capability; see the Typical Performance

Characteristics section.

Note 6: See output current derating curves for different VIN, VOUT, and TA,

located in the Applications Information section.

Note 7: Even though VOUT0 and VOUT1 are specified for 6V absolute

maximum, the maximum recommended regulation-command voltage is:

3.6V for a high-VOUT range setting of MFR_PWM_MODEn[1] = 0b; 2.5V

for a low-VOUT range setting of MFR_PWM_MODEn[1] = 1b.

Note 8: Minimum on-time is tested at wafer sort.

Note 9: Data conversion is performed in round-robin (cyclic) fashion.

All telemetry signals are continuously digitized, and reported data is

based on measurements not older than 90ms, typical. Some telemetry

parameters can be digitized at a faster update rate by configuring

MFR_ADC_CONTROL.

Note 10: The following telemetry parameters are formatted in PMBus-

defined “Linear Data Format”, in which each register contains a word

comprised of 5 most significant bits—representing a signed exponent, to

be raised to the power of 2—and 11 least significant bits—representing

a signed mantissa: input voltage (on SVIN), accessed via the READ_VIN

command code; output currents (IOUTn), accessed via the READ_IOUTn

command codes; module input current (IVIN0 + IVIN1 + ISVIN), accessed via

the READ_IIN command code; channel input currents (IVINn + 1/2 • ISVIN),

accessed via the MFR_READ_IINn command codes;and duty cycles of

channel 0 and channel 1 switching power stages, accessed via the

READ_DUTY_CYCLEn command codes. This data format limits the

resolution of telemetry readback data to 10 bits even though the internal

ADC is 16 bits and the LTM4686B’s internal calculations use 32-bit words.

Note 11: The absolute maximum rating for the SVIN pin is 6V. Input

voltage telemetry (READ_VIN) is obtained by digitizing a voltage scaled

down from the SVIN pin.

Note 12: These typical parameters are based on bench measurements and

are not production tested.

Note 13: EEPROM endurance and retention are guaranteed by wafer-level

testing for data retention. The minimum retention specification applies

for devices whose EEPROM has been cycled less than the minimum

endurance specification, and whose EEPROM data was written to at

0°C ≤ TJ ≤ 85°C. Downloading NVM contents to RAM by executing

the RESTORE_USER_ALL or MFR_RESET commands is valid over the

entire operating temperature range and does not influence EEPROM

characteristics.

Note 14: Channel 0 OV/UV comparator threshold accuracy for

MFR_PWM_MODE0[1] = 1b tested in ATE at VVOSNS0+ – VVOSNS0– =

0.5V and 2.7V. Channel 0’s 1V test corner condition is tested at

IC-level, only. Channel 1 OV/UV comparator threshold accuracy for

MFR_PWM_MODE1[1] = 1b tested in ATE with VVOSNS1 to VSGND = 0.5V

and 2.7V. Channel 1’s 1.5V test corner condition is tested at IC-level, only.

Note 15: Tested at IC-level ATE.

Note 16: PLL SYNC capture range tested with FREQUENCY_SWITCH set to

frequency slave mode (0x0000), with MFR_CONFIG_ALL[4] = 1b, and with

SYNC driven by external clock. Low end of SYNC capture range (450kHz)

verified at VINn = 2.375V and VOUTn = 0.5V. High end of SYNC capture

range (1.05MHz) verified at VIN = 5V and VOUTn = 3.3V.

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