LTM4686BEVPBF datasheet(54/130 Pages) AD

54 / 130 page

LTM4686B

Rev. 0

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APPLICATIONS INFORMATION

be asserted low, indicating that NVM has not initialized.

If this condition is detected, the part will only respond to

addresses 0x5A and 0x5B. To initialize the part issue the

following set of commands: global address 0x5B com-

mand 0xBD data 0x2B followed by global address 0x5B

command 0xBD and data 0xC4. The part will now respond

to the correct address. Configure the part as desired

then issue a STORE_USER_ALL. When SVIN is applied a

MFR_RESET or RESTORE_USER_ALL, command must

be issued to allow the PWM to be enabled and valid ADC

conversions to be read.

FAULT DETECTION AND HANDLING

The LTM4686B GPIOn pins are configurable to indi-

cate a variety of faults including OV/UV, OC, OT, timing

faults, peak overcurrent faults. In addition the GPIOn pins

can be pulled low by external sources to indicate to the

LTM4686B the presence of a fault in some other portion of

the system. The fault response is configurable via PMBus

Command Code names with a _RESPONSE suffix and

allows the following options:

Ignore

Shut Down Immediately—Latch Off

Shut Down Immediately—Retry Indefinitely at the Time

Interval Specified in MFR_RETRY_DELAYn

Refer to Appendix C and the PMBus specification for more

details.

The OV response is automatic and rapid. If an OV is

detected, MTn is turned off and BGn is turned on, until

the OV condition clears.

Fault logging is available on the LTM4686B. The fault log-

ging is configurable to automatically store data when a

fault occurs that causes the unit to fault off. The header

portion of the fault logging table contains peak values. It

is possible to read these values at any time. This data will

be useful while troubleshooting the fault.

If the LTM4686B internal temperature is in excess of 85°C

or below 0°C, the write into the NVM is not recommended.

The data will still be held in RAM, unless the 3.3V supply

UVLO threshold is reached. If the die temperature exceeds

130°C all NVM communication is disabled until the die

temperature drops below 125°C, with the exception of

the RESTORE_USER_ALL command, which is valid at

any temperature.

OPEN-DRAIN PINS

Note that up to nine pull-up resistors are required for

proper operation of the LTM4686B:

• Three for the SMBus/I2C interface (the SCL, SDA, and

ALERT pins); two, only if the system SMBus host does

not make use of the ALERT interrupt. (These are 5V

tolerant).

• One each for the RUN0 and RUN1 pins (or, just one to

RUN0 and RUN1, if RUN0 and RUN1 are electrically

connected together). (These are 5V tolerant).

• One each for GPIO0 and GPIO1 (or, just one to GPIO0

and GPIO1, if GPIO0 and GPIO1 are electrically con-

nected together). (These are 3.3V tolerant).

• One on SHARE_CLK, required, for the LTM4686B to

establish a heartbeat time base for timing-related oper-

ations and functions (output voltage ramp-up timing,

voltage margining transition timing, SYNC open-drain

drive frequency). (SHARE CLK is 3.3V tolerant).

• One on SYNC, in order for the LTM4686B to phase lock

to the frequency generated by the open-drain output

of its digital engine. EXCEPTION: in some applications,

it is desirable to drive the LTM4686B’s SYNC pin with

a hard-driven (low impedance) external clock. This

is the only scenario where the LTM4686B does not

require a pull-up resistor on SYNC. However, be aware

that the SYNC pin can be low impedance during NVM

initialization, i.e., during download of EEPROM con-

tents to RAM (for ~50ms [Note 12] after SVIN power is

applied). Therefore, the hard-driven clock signal should

only be applied to the LTM4686B SYNC pin through a

series resistor whose impedance limits current into

the SYNC pin during NVM initialization to less than

10mA. If FREQUENCY_SWITCH = 0x0000, any clock

signal should be provided prior to the RUNn pins toggle

from logic low to logic high, or else the switching fre-

quency of the LTM4686B will start off at the low end

of its PLL-capture range until the SYNC clock becomes

established. (SYNC is 3.3V tolerant).

LTM4686BEVPBF 数据表(PDF) 54 Page - Analog Devices

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