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LTM4686BEVPBF 数据表(PDF) 22 Page - Analog Devices

部件名 LTM4686BEVPBF
功能描述  Ultrathin Dual 14A or Single 28A 關Module Regulator with Digital Power System Management
PDF  130 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

LTM4686BEVPBF 数据表(HTML) 22 Page - Analog Devices

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LTM4686B
22
Rev. 0
For more information www.analog.com
OPERATION
n
Three Integrated Temperature Sensors, Over/
Undertemperature Protection.
n
Constant Frequency Peak Current Mode Control.
n
Configurable Switching Frequency, 500kHz to 1MHz;
Synchronizable to External Clock; Seven Configurable
Channel Phase Interleaving Settings.
n
Internal Loop Compensation Provided; External Loop
Compensation Can Be Applied, if Preferred.
n
Low Profile (16mm × 11.9mm × 1.82mm) LGA Package
Power Solution Requires Only Input and Output
Capacitors; at Most, Nine Pull-Up Resistors for Open-
Drain Digital Signals; at Most, Six Pull-Down Resistors
to Configure All Possible Pin-Strapping Options.
Features of the LTM4686B that enable power system
management, rail sequencing, and fault monitoring and
reporting are as follows:
n
I2C-based PMBus/SMBus 2-Wire Serial Communication
Interface (SDA, SCL) with ALERT Interrupt Pin, SCL
Clock Capable of 400kHz Bus Communication Speeds
with Clock Low Extending—or 100kHz, Otherwise.
n
Configurable Output Voltage.
n
Configurable Input Undervoltage Comparators (UVLO
Rising, UVLO Falling).
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Configurable Switching Frequency.
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Configurable Current Limit.
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Configurable Output Over/Undervoltage Comparators.
n
Configurable Turn-On and Turn-Off Delay Times.
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Configurable Output Ramp Rise and Fall Times.
n
Nonvolatile Configuration Memory (NVM EEPROM)
with ECC to Configure Aforementioned Settings, and
More—Yielding Standalone Operation, if Desired, and
Also Enabling In-Situ Changes to the LTM4686B’s
Configuration in Embedded Designs.
n
Monitoring and Reporting of Telemetry Data: Average
Output and Input Currents and Voltages, Internal
Temperatures, and Power Stage Duty Cycles—
Continuously Digitized Cyclically by a 16-Bit ADC.
• Peak Observed Output Current and Voltage, Input
Voltage, and Module Temperatures Can Be Polled
and Cleared/Reset.
• ADC Latency Not Greater Than 90ms, Nominal.
• Option to Monitor One External Temperature in Lieu of
Channel 1 (VOUT1) Module Power Stage Temperature.
n
Monitoring, Reporting, and Configurable Response
to Latching and Non-Latching Individual Fault and/or
Warning Status, Including but Not Limited to:
• Output Over/Undervoltages.
• Input (SVIN) Over/Undervoltages.
• Module Input and Power Stage Output Overcurrents.
• Module Power Stage Over/Under Temperatures.
• Internal Control IC Overtemperature.
• Communication, Memory and Logic (CML) Faults.
n
Fault Logging Upon Detection of a Fault Condition. The
LTM4686B Can Be Configured to Automatically Upload a
Fault Log to Its NVM, Consisting of: an Uptime Counter,
Peak Observed Telemetry, Telemetry Gathered from the Six
Most Recent Rounds of Cyclical ADC Data Leading Up to
the Detection of the Fault That Triggered Fault Log Writing,
and Fault Status Associated with That ADC History.
n
Two Configurable Open-Drain General Purpose Input/
Output Pins (GPIO0, GPIO1), Which Can Be Used for:
• Fault Reporting, e.g., as a System Interrupt Signal.
• Coordinating Turn-On/Off of the LTM4686B in
Multiphase/Multirail Systems.
• Propagating an Unfiltered Power Good Signal
(Output of a VOUTn Undervoltage Comparator) to
Command Turn-On/Off of a Downstream Rail.
n
A Write Protect (WP) Pin and Configurable
WRITE_PROTECT Register to Protect the Internal
Configuration of RAM and NVM Against Unintended
Changes via I2C.
n
Time-Base Interconnect (SHARE_CLK, 100kHz
Heartbeat) for Synchronization in the Time Domain
Between Multiple LTM4686Bs.
n
Optional External Configuration Resistors (RCONFIGs) for
Setting Start-Up Output Voltages, Switching Frequency
and Channel-to-Channel Phase Interleaving Angle.
n
Any 7-Bit Slave Address Can Be Assigned to the
LTM4686B (0x4F Default), Configured by Resistor Pin
Strapping the ASEL Pin and User-Editable Bits [6:4] of
MFR_ADDRESS.



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