LTM4686BEVPBF datasheet(50/130 Pages) AD

50 / 130 page

LTM4686B

Rev. 0

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APPLICATIONS INFORMATION

The relative phasing of all active channels in a PolyPhase

rail should be optimally phased. The relative phasing of

each rail is 360°/n, where n is the number of phases in

the rail. MFR_PWM_CONFIG[2:0] configures channel

relative phasing with respect to the SYNC pin. Phase

relationship values are indicated with 0° corresponding

to the falling edge of SYNC being coincident with the

turn-on of the top MOSFETs, MTn.

The MFR_PWM_CONFIG command can be altered

via I2C commands, but only when switching action is

disengaged, i.e., the module’s outputs are turned off. The

MFR_PWM_CONFIG command takes on the value stored

in NVM at SVIN power-up, but is overridden according

to a resistor pin-strap applied between the FSWPHCFG pin

and SGND only if the module is configured to respect

resistor pin-strap settings (MFR_CONFIG_ALL[6] =

0b). Table 4 highlights available resistor pin-strap and

corresponding MFR_PWM_CONFIG[2:0] settings.

Some combinations of FREQUENCY_SWITCH and

MFR_PWM_CONFIG[2:0] are not available by resistor

pin-strapping the FSWPHCFG pin. All combinations

of supported values for FREQUENCY_SWITCH and

MFR_PWM_CONFIG[2:0] can be configured by NVM

programming—or, I2C transactions, provided switching

action is disengaged, i.e., the module’s outputs are

turned off.

Care must be taken to minimize capacitance on SYNC

to assure that the pull-up resistor versus the capacitor

load has a low enough time constant for the application

to form a “clean” clock. (See “Open-Drain Pins”, later

in this section.)

When an LTM4686B is configured as a sync slave, it is

permissible for external circuitry to drive the SYNC pin

from a current-limited source (less than 10mA), rather

than using a pull-up resistor. Any external circuitry

must not drive high with arbitrarily low impedance at

SVIN power-up, because the SYNC output can be low

impedance until NVM contents have been downloaded

to RAM.

Recommended LTM4686B switching frequencies of

operation for many common VIN-to-VOUT applications

are indicated in Table 7. When the two channels of an

LTM4686B are stepping input voltage(s) down to output

voltages whose recommended switching frequencies in

Table 7 are significantly different, operation at the higher of

the two recommended switching frequencies is preferable,

but minimum on-time must be considered. (See Minimum

On-Time Considerations section.) For example, consider an

application in which it is desired for an LTM4686B to step-

down 5VIN to 0.6VOUT on Channel 0, and 5VIN to 3.3VOUT

on Channel 1: according to Table 7, the recommended

switching frequency is 500kHz and 1MHz, respectively.

However, the switching frequency setting of the LTM4686B

is common to both channels. Based on the aforementioned

guidance, operation at 1MHz would be preferred—in order

to keep inductor ripple currents reasonable. The on-time for

a 5VIN-to-0.6VOUT conditionat1MHzis120ns,thusmeeting

the 90ns guardband recommendation. Therefore, for this

particular example, the recommended switching frequency

becomes 1MHz.

Table 7. Recommended Switching Frequency for Various

VIN-to-VOUT Step-Down Scenarios

2.5VIN

3.3VIN

5VIN

0.6VOUT

425kHz

500kHz

0.7VOUT

500kHz

575kHz

0.8VOUT

500kHz

575kHz

650kHz

0.9VOUT

575kHz

650kHz

1VOUT

575kHz

650kHz

750kHz

1.2VOUT

575kHz

750kHz

1MHz

1.5VOUT

575kHz

750kHz

1MHz

1.8VOUT

575kHz

750kHz

1MHz

2.5VOUT

N/A

650kHz

1MHz

3.3VOUT

N/A

1MHz

The current drawn by the SVIN pin of the LTM4686B is

not digitized or computed. A value representing the esti-

mated SVIN current is located in the MFR_IIN_OFFSETn

command, and is used in the computations of input

current readback telemetry, namely READ_IIN and and

MFR_READ_IINn. The recommended setting of MFR_IIN_

OFFSETn is found in Table 8. The same value should be

used for MFR_IIN_OFFSET0 and MFR_IIN_OFFSET1 (i.e.,

Pages 0x00 and 0x01).

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