LTM4686BEVPBF datasheet(33/130 Pages) AD

33 / 130 page

LTM4686B

Rev. 0

For more information www.analog.com

OPERATION

The integrity of the EEPROM is checked with a CRC calcu-

lation each time its data is read, such as after a power-on

reset or execution of a RESTORE_USER_ALL or MFR_

RESET command. If CRC error occurs, the MFR bit is set

in the STATUS_BYTE and STATUS_WORD commands.

The NVM CRC error bit in the STATUS_MFR_SPECIFIC

command is set and the ALERT and RUN pins are pulled

low disabling the output as a safety measure. The device

will only respond at special address 0x7C or global

addresses 0x5A and 0x5B.

Internal EEPROM with CRC Protection and ECC

The LTM4686B contains internal EEPROM with Error

Correction Coding (ECC) to store user configuration set-

tings and fault log information. EEPROM endurance and

retention for user space and fault log pages are speci-

fied in the Absolute Maximum Ratings and Electrical

Characteristics table.

The integrity of the EEPROM memory is checked with a

CRC calculation each time its data is to be read, such as

after a power-on reset. A CRC error will prevent the con-

troller from leaving the OFF state. If a CRC error occurs, the

CML bit is set in the STATUS_BYTE and STATUS_WORD

commands, the appropriate bit is set in the STATUS_MFR_

SPECIFIC command, and the ALERT and RUN pins will be

pulled low. At that point the device will respond at special

address 0x7C, which is only activated after an invalid CRC

has been detected. The module will also respond to global

addresses 0x5A and 0x5B, but all ADI PSM modules and

ICs will respond to these addresses so users must be

careful when using global addresses. EEPROM repair can

be attempted by writing the desired configuration to the

controller and executing a STORE_USER_ALL command

followed by a CLEAR_FAULTS command. Contact the fac-

tory if EEPROM repair is unsuccessful.

See the Applications Information section and Analog

Devices Application Note 145, or contact the factory

for details on efficient in-system EEPROM program-

ming, including bulk EEPROM programming, which the

LTM4686B also supports.

SERIAL INTERFACE

The LTM4686B serial interface is a PMBus compliant slave

device and can operate at any frequency between 10kHz

and 400kHz. The address is configurable using either the

EEPROM or an external resistor. In addition the LTM4686B

always responds to the global broadcast address of 0x5A

(7 bit) or 0x5B (7 bit). Address 0x5A is not paged and

is performed on both channels. 0x5B respects the page

command. Because address 0x5A does not support page,

it can not be used for any paged reading commands.

The serial interface supports the following protocols

defined in the PMBus specifications: 1) send command,

2) write byte, 3) write word, 4) group, 5) read byte, 6)

read word and 7) read block 8) PAGE_PLUS_READ, 9)

PAGE_PLUS_WRITE 10) SMBALERT_MASK read, 11)

SMBALERT_MASK write. All read operations will return

a valid PEC if the PMBus master requests it. If the PEC_

REQUIRED bit is set in the MFR_CONFIG_ALL command,

the PMBus write operations will not be acted upon until a

valid PEC has been received by the LTM4686B.

Communication Protection

PEC write errors (if PEC_REQUIRED is active), attempts

to access unsupported commands, or writing invalid data

to supported commands will result in a CML fault. The

CML bit is set in the STATUS_BYTE and STATUS_WORD

commands, the appropriate bit is set in the STATUS_CML

command, and the ALERT pin is pulled low.

DEVICE ADDRESSING

The LTM4686B offers four different types of addressing

over the PMBus interface, specifically: 1) global, 2) device,

3) rail addressing and 4) alert response address (ARA).

Global addressing provides a means of the PMBus master to

address all LTM4686B devices on the bus. The LTM4686B

globaladdressisfixed0x5A(7bit)or0xB4(8bit)andcannot

be disabled. Commands sent to the global address act the

same as if PAGE is set to a value of 0xFF. Commands sent are

written to both channels simultaneously. Global command

0x5B (7 bit) or 0xB6 (8 bit) is paged and allows channel spe-

cific command of all LTM4686B devices on the bus. Other

ADI device types may respond at one or both of these global

addresses;thereforedonotreadfromglobaladdresses.

LTM4686BEVPBF 数据表(PDF) 33 Page - Analog Devices

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