LTM4686BEVPBF datasheet(51/130 Pages) AD

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LTM4686B

Rev. 0

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APPLICATIONS INFORMATION

Table 8. Recommended MFR_IIN_OFFSETn Setting vs

Switching Frequency Setting

SWITCHING

FREQUENCY

(kHz)

FREQUENCY_

SWITCH

COMMAND

VALUE (HEX.)

RECOMMENDED

MFR_IIN_

OFFSETn

SETTING (mA)

RECOMMENDED

MFR_IIN_

OFFSETn

SETTING (HEX.)

500

0xFBE8

29.56

0x8BC9

575

0x023F

32.35

0x9212

650

0x028A

35.14

0x9240

750

0x02EE

38.86

0x927D

1000

0x03E8

48.16

0x9315

Sync. to

External Clock,

fSYNC

N/A

0.0372 • fSYNC +

10.96

*See Appendix C: PMBus Command Details, L11 data format.

MINIMUM ON-TIME CONSIDERATIONS

Minimum on-time, tON(MIN), is the smallest time dura-

tion that the LTM4686B is capable of turning on the top

MOSFET. It is determined by internal timing delays and

the gate charge required to turn on the top MOSFET. Low

duty cycle applications may approach this minimum on-

time limit and care should be taken to ensure Equation 6.

tON(MIN) <

VOUTn

VINn • fOSC

(6)

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

The minimum on-time for the LTM4686B is 45ns, nomi-

nal, guardband to 90ns.

VARIABLE DELAY TIME, SOFT-START AND OUTPUT

VOLTAGE RAMPING

The LTM4686B must enter its run state prior to soft-start.

The RUNn pins are released after the part initializes and

SVIN is greater than the VIN_ON threshold. If multiple

LTM4686Bs are used in an application, they should be

configured to share the same RUNn pins. They all hold

their respective RUNn pins low until all devices initialize

and SVIN exceeds the VIN_ON threshold for all devices.

The SHARE_CLK pin assures all the devices connected to

the signal use the same time base.

After the RUNn pin releases, the controller waits for the

user-specified turn-on delay (TON_DELAYn) prior to ini-

tiating an output voltage ramp. Multiple LTM4686Bs and

other ADI parts can be configured to start with variable

delay times. To work correctly, all devices use the same

timing clock (SHARE_CLK) and all devices must share

the RUNn pin. This allows the relative delay of all parts to

be synchronized. The actual variation in the delay will be

dependent on the highest clock rate of the devices con-

nected to the SHARE_CLK pin (all Analog Devices, ICs

are configured to allow the fastest SHARE_CLK signal to

control the timing of all devices). The SHARE_CLK signal

can be ±5% in frequency, thus the actual time delays will

have some variance.

Soft-start is performed by actively regulating the load

voltage while digitally ramping the target voltage from 0V

to the commanded voltage set point. The rise time of the

voltage ramp can be programmed using the TON_RISEn

command to minimize inrush currents associated with the

start-up voltage ramp. The soft-start feature is disabled

by setting TON_RISEn to any value less than 0.250ms.

The LTM4686B performs the necessary math internally to

assure the voltage ramp is controlled to the desired slope.

However, the voltage slope can not be any faster than the

fundamental limits of the power stage. The number of steps

in the ramp is equal to TON_RISE/0.1ms. Therefore, the

shorter the TON_RISEn time setting, the more jagged the

soft-start ramp appears.

The LTM4686B PWM always operates in discontinuous

mode during the TON_RISEn operation. In discontinuous

mode, the bottom MOSFET (MBn) is turned off as soon

as reverse current is detected in the inductor. This allows

the regulator to start up into a prebiased load.

There is no analog tracking feature in the LTM4686B;

however, two outputs can be given the same TON_RISEn

and TON_DELAYn times to achieve ratiometric rail track-

ing. Because the RUNn pins are released at the same time

and both units use the same time base (SHARE_CLK), the

outputs track very closely. If the circuit is in a PolyPhase

configuration, all timing parameters must be the same.

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