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LTM4686BEVPBF 数据表(PDF) 84 Page - Analog Devices |
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LTM4686BEVPBF 数据表(HTML) 84 Page - Analog Devices |
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84 / 130 page  LTM4686B 84 Rev. 0 For more information www.analog.com If WP pin is high, PAGE, OPERATION, MFR_CLEAR_PEAKS, MFR_EE_UNLOCK and CLEAR_FAULTS commands are supported. Individual fault bits can be cleared by writing a 1 to the respective bits in the STATUS registers. MFR_ADDRESS The MFR_ADDRESS command byte sets the 7 bits of the PMBus slave address for this device. Setting this command to a value of 0x80 disables device addressing. The GLOBAL device address, 0x5A and 0x5B, cannot be deactivated. If RCONFIG is set to ignore (MFR_CONFIG_ALL[6] = 1b), the ASEL pin is still used to determine the LSB of the channel address. If the ASEL pin is open, the LTM4686B will use the MFR_ADDRESS stored in EEPROM. Values of 0x5A, 0x5B, 0x0C, and 0x7C are not recommended. This command has one data byte. MFR_RAIL_ADDRESS The MFR_RAIL_ADDRESS command enables direct device address access to the PAGE activated channel. The value of this command should be common to all devices attached to a single power supply rail. The user should only perform command writes to this address. If a read is performed from this address and the rail devices do not respond with EXACTLY the same value, the LTM4686B will detect bus contention and set a CML com- munications fault. Setting this command to a value of 0x80 disables rail device addressing for the channel. This command has one data byte. GENERAL CONFIGURATION REGISTERS COMMAND NAME CMD CODE DESCRIPTION TYPE PAGED DATA FORMAT UNITS NVM DEFAULT VALUE MFR_CHAN_CONFIG 0xD0 Configuration bits that are channel specific. R/W Byte Y Reg Y 0x1D MFR_CONFIG_ALL 0xD1 Configuration bits that are common to all pages. R/W Byte N Reg Y 0x09 MFR_CHAN_CONFIG General purpose configuration command common to multiple ADI products. BIT MEANING 7 Reserved 6 Reserved 5 Reserved 4 Disable RUN Low. When asserted the RUN pin is not pulsed low if commanded OFF 3 Short Cycle. When asserted the output will immediate off if commanded ON while waiting for TOFF_DELAY or TOFF_FALL. TOFF_MIN of 120ms is honored then the part will command ON. 2 SHARE_CLOCK control, if SHARE_CLOCK is held low, the output is disabled 1 No GPIO ALERT, ALERT is not pulled low if GPIO is pulled low externally. Assert this bit if either POWER_GOOD or VOUT_UVUF are propagated on GPIO 0 Disables the VOUT decay value requirement for MFR_RETRY_TIME processing. When this bit is set to a 0, the output must decay to less than 12.5% of the programmed value for any action that turns off the rail including a fault, an OFF/ON command, or a toggle of RUN from high to low to high. This command has one data byte. APPENDIX C: PMBUS COMMAND DETAILS |
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