LTM4686BEVPBF datasheet(55/130 Pages) AD

55 / 130 page

LTM4686B

Rev. 0

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APPLICATIONS INFORMATION

All the above pins interface to pull-down transistors

within the module that can sink 3mA at 0.4V. The low

threshold on the pins is 0.8V; thus, plenty of margin

on the digital signals with 3mA of current. For 3.3V

pins, 3mA of current is a 1.1k resistor. Unless there

are transient speed issues associated with the RC time

constant of the resistor pull-up and parasitic capaci-

tance to ground, a 10k resistor or larger is generally

recommended.

For high speed signals such as the SDA, SCL and SYNC,

a lower value resistor may be required. The RC time con-

stant should be set to 1/3 to 1/5 the required rise time

to avoid timing issues. For a 100pF load and a 400kHz

PMBus communication rate, the rise time must be less

than 300ns. The resistor pull-up on the SDA and SCL

pins with the time constant set to 1/3 the rise time is

give by Equation 4.

RPULLUP =

tRISE

3•100pF

=1k

(4)

Be careful to minimize parasitic capacitance on the SDA

and SCL pins to avoid communication problems. To esti-

mate the loading capacitance, monitor the signal in ques-

tion and measure how long it takes for the desired signal

to reach approximately 63% of the output value. This is

one time constant.

The SYNC pin interfaces to a pull-down transistor within

the module whose output is held low for nominally 500ns

per switching period. If the internal oscillator is set for

500kHz and the load is 100pF and a 3x time constant is

required, the resistor calculation is given by Equation 5.

RPULLUP =

2µs– 500ns

3•100pF

= 5k

(5)

The closest 1% resistor is 4.99k.

If timing errors are occurring or if the SYNC frequency is

not as fast as desired, monitor the waveform and deter-

mine if the RC time constant is too long for the application.

If possible reduce the parasitic capacitance. If not reduce

the pull up resistor sufficiently to assure proper timing.

PHASE-LOCKED LOOP AND FREQUENCY

SYNCHRONIZATION

The LTM4686B has a phase-locked loop (PLL) comprised

of an internal voltage-controlled oscillator (VCO) and a

phase detector. The PLL is locked to the falling edge of

the SYNC pin. The phase relationship between channel 0,

channel 1 and the falling edge of SYNC is controlled by

the lower 3 bits of the MFR_PWM_CONFIG command. For

PolyPhase applications, it is recommended all the phases

be spaced evenly. Thus for a 2-phase system the signals

should be 180° out of phase and a 4-phase system should

be spaced 90°.

The phase detector is an edge-sensitive digital type that

provides a known phase shift between the external and

internal oscillators. This type of phase detector does not

exhibit false lock to harmonics of the external clock.

The output of the phase detector is a pair of complemen-

tary current sources that charge or discharge the internal

filter network. The PLL lock range is guaranteed between

450kHz and 1.05MHz.

The PLL has a lock detection circuit. If the PLL should

lose lock during operation, bit 4 of the STATUS_MFR_

SPECIFIC command is asserted and the ALERT pin is

pulled low. The fault can be cleared by writing a 1 to

the bit. If the user does not wish to see the PLL_FAULT,

even if a synchronization clock is not available at power

up, bit 3 of the MFR_CONFIG_ALL command must be

asserted.

If the SYNC signal is not clocking in the application, the

PLL runs at the lowest free running frequency of the VCO.

This will be well below the intended PWM frequency of

the application and may cause undesirable operation of

the converter.

If the PWM (SWn) signal appears to be running at too

high a frequency, monitor the SYNC pin. Extra transitions

on the falling edge will result in the PLL trying to lock on

to noise instead of the intended signal. Review routing of

digital control signals and minimize crosstalk to the SYNC

signal to avoid this problem. Multiple LTM4686Bs are

required to share the SYNC pin in PolyPhase configura-

tions; for other configurations, it is optional. If the SYNC

LTM4686BEVPBF 数据表(PDF) 55 Page - Analog Devices

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