LTM4686BEVPBF datasheet(31/130 Pages) AD

31 / 130 page

LTM4686B

Rev. 0

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OPERATION

Output power readback is computed by the LTM4686B

according to:

READ_POUTn = READ_VOUTn • READ_IOUTn

Alternating excitation currents of 2µA and 30µA are

sourced from the TSNS1a pin. Connecting TSNS1a to

TSNS1b, temperature sensing of the Channel 1 power

stage is realized by the LTM4686B digitizing the voltages

that appear at the PNP transistor temperature sensor that

resides at the TSNS1b pin. Analogous activity occurs on

the TSNS0 node, from which Channel 0 power stage

temperature is derived. The LTM4686B performs what is

known in the industry as delta VBE (∆VBE) computations

and makes channel (power stage) temperature telemetry

available over I2C (READ_TEMPERATURE_1n). The junc-

tion temperature of the control IC within the LTM4686B

is also available over I2C (READ_TEMPERATURE_2).

Observed peak Channel temperatures can be read back

in registers READ_MFR_TEMPERATURE_1_PEAKn.

Observed peak temperature of the control IC can be read

back in register MFR_READ_TEMPERATURE_2_PEAK.

For a fixed load current, the amplitude of the current

sense information changes over temperature due to the

temperature coefficient of copper (inductor DCR), which

is approximately 3900ppm/°C. This would introduce sig-

nificant current readback error over the operating range

of the module if not for the fact that the LTM4686B’s tem-

perature readback information is used in conjunction with

the perceived current sense signal to yield temperature-

corrected current readback data.

If desired, it is possible to use only the temperature

readback information derived by the TSNS0 pin to yield

temperature-corrected current readback data for both

Channels 0 and 1. This frees up the Channel 1 tempera-

ture sensor to monitor a temperature sensor external to

the LTM4686B. This is achieved by setting MFR_PWM_

MODE0[4] = 1b (the NVM-factory default value is 0b).

This degrades the current readback accuracy of Channel

1—more so when Channel 0 and Channel 1 are not paral-

leled outputs. However, the TSNS1a pin becomes available

to be connected to an external diode-connected small-

signal PNP transistor (such as 2N3906) and 10nF X7R

capacitor, i.e., an external temperature sensor, whose

temperature readback data and peak value are avail-

able over I2C (READ_TEMPERATURE_11, MFR_READ_

TEMPERATURE_1_PEAK1). Implementation of the

aforementioned is as follows: (1) local to the LTM4686B,

electrically connect a 10nF X7R capacitor directly from

TSNS1a to SGND; (2) differentially route a pair of traces

from the LTM4686B’s TSNS1a and SGND pins to the tar-

get PNP transistor; (3) electrically connect the emitter of

the PNP transistor to TSNS1a; (4) electrically connect the

collector and base of the PNP transistor to SGND.

Power stage duty cycle readback telemetry is available

over I2C (READ_DUTY_CYCLEn registers). Computed

channel input current readback is computed by the

LTM4686B as:

MFR_READ_IINn = READ_DUTY_CYCLEn • READ_IOUTn

+ MFR_IIN_OFFSETn

Computed module input current readback is computed

by the LTM4686B as:

READ_IIN = MFR_READ_IIN0 + MFR_READ_IIN1

where MFR_IIN_OFFSETn is a register value represent-

ing the SVIN input bias current. The SVIN current is not

digitized by the module. The factory NVM-default value of

MFR_IIN_OFFSETn is 48.16mA, representing the contribu-

tion of current drawn by each of the module’s channels

on the SVIN pin, when the power stages are operating

in forced continuous mode at the factory-default switch-

ing frequency of 1MHz. See Table 8 in the Applications

Information section for recommended MFR_IIN_OFFSETn

setting vs Switching Frequency. The aforementioned

method by which input current is calculated yields an

accurate current readback value even at light load currents,

but only as long as the module is configured for forced

continuous operation (NVM-factory default). SVIN and

peak SVIN readback telemetry is accessible via I2C in the

READ_VIN and MFR_VIN_PEAK registers, respectively.

The power stage switch nodes are brought out on the

SWn pin for functional operation monitoring and for

optional installation of a resistor-capacitor snubber circuit

(terminated to GND) for reduced EMI.

The LTM4686B features a write protect (WP) pin. If WP is

open circuit or logic high, I2C writes are severely restricted:

LTM4686BEVPBF 数据表(PDF) 31 Page - Analog Devices

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