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AM2434...ALV 数据表(PDF) 141 Page - Texas Instruments |
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AM2434...ALV 数据表(HTML) 141 Page - Texas Instruments |
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141 / 280 page ![]() 7.10.3.3 Clock Timing Tables and figures provided in this section define timing requirements and switching characteristics for clock signals. Table 7-15. Clock Timing Requirements see Figure 7-14 NO. MIN MAX UNIT CLK1 tc(EXT_REFCLK1) Cycle time minimum, EXT_REFCLK1 10 ns CLK2 tw(EXT_REFCLK1H) Pulse Duration minimum, EXT_REFCLK1 high E*0.45(1) E*0.55(1) ns CLK3 tw(EXT_REFCLK1L) Pulse Duration minimum, EXT_REFCLK1 low E*0.45(1) E*0.55(1) ns CLK19 tc(MCU_EXT_REFCLK0) Cycle time minimum, MCU_EXT_REFCLK0 10 ns CLK20 tw(MCU_EXT_REFCLK0H) Pulse Duration minimum, MCU_EXT_REFCLK0 high F*0.45(2) F*0.55(2) ns CLK21 tw(MCU_EXT_REFCLK0L) Pulse Duration minimum, MCU_EXT_REFCLK0 low F*0.45(2) F*0.55(2) ns (1) E = EXT_REFCLK1 cycle time (2) F = MCU_EXT_REFCLK0 cycle time EXT_REFCLK1 CLK1 CLK2 CLK3 CLK19 CLK20 CLK21 MCU_EXT_REFCLK0 Figure 7-14. Clock Timing Requirements Table 7-16. Clock Switching Characteristics see Figure 7-15 NO. PARAMETER MIN MAX UNIT CLK4 tc(SYSCLKOUT0) Cycle time minimum,SYSCLKOUT0 8 ns CLK5 tw(SYSCLKOUT0H) Pulse Duration minimum, SYSCLKOUT0 high A*0.4(1) A*0.6(1) ns CLK6 tw(SYSCLKOUT0L) Pulse Duration minimum, SYSCLKOUT0 low A*0.4(1) A*0.6(1) ns CLK7 tc(OBSCLK0) Cycle time minimum, OBSCLK0 5 ns CLK8 tw(OBSCLK0H) Pulse Duration minimum, OBSCLK0 high B*0.45(2) B*0.55(2) ns CLK9 tw(OBSCLK0L) Pulse Duration minimum,OBSCLK0 low B*0.45(2) B*0.55(2) ns CLK10 tc(CLKOUT0) Cycle time minimum, CLKOUT0 20 ns CLK11 tw(CLKOUT0H) Pulse Duration minimum, CLKOUT0 high C*0.4(3) C*0.6(3) ns CLK12 tw(CLKOUT0L) Pulse Duration minimum,CLKOUT0 low C*0.4(3) C*0.6(3) ns CLK13 tc(MCU_SYSCLKOUT0) Cycle time minimum, MCU_SYSCLKOUT0 10 ns CLK14 tw(MCU_SYSCLKOUT0H) Pulse Duration minimum, MCU_SYSCLKOUT0 high G*0.4(4) G*0.6(4) ns CLK15 tw(MCU_SYSCLKOUT0L) Pulse Duration minimum,MCU_SYSCLKOUT0 low G*0.4(4) G*0.6(4) ns CLK16 tc(MCU_OBSCLK0) Cycle time minimum, MCU_OBSCLK0 5 ns CLK17 tw(MCU_OBSCLK0H) Pulse Duration minimum, MCU_OBSCLK0 high H*0.45(5) H*0.55(5) ns CLK18 tw(MCU_OBSCLK0L) Pulse Duration minimum,MCU_OBSCLK0 low H*0.45(5) H*0.55(5) ns (1) A = SYSCLKOUT0 cycle time (2) B = OBSCLK0 cycle time (3) C = CLKOUT0 cycle time (4) G = MCU_SYSCLKOUT0 cycle time (5) H = MCU_OBSCLK0 cycle time www.ti.com AM2434, AM2432, AM2431 SPRSP65D – APRIL 2021 – REVISED AUGUST 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 141 Product Folder Links: AM2434 AM2432 AM2431 |
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