AM2434...ALV datasheet(214/280 Pages) TI

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Table 7-95. OSPI Switching Characteristics – PHY Data Training

See Figure 7-80

NO.

PARAMETER

MODE

MIN

MAX

UNIT

tc(CLK)

Cycle time, OSPI0_CLK

1.8V, DDR

6.02

3.3V, DDR

7.52

tw(CLKL)

Pulse duration, OSPI0_CLK low

DDR

((0.475P(1)) - 0.3)

tw(CLKH)

Pulse duration, OSPI0_CLK high

DDR

((0.475P(1)) - 0.3)

td(CSn-CLK)

Delay time, OSPI0_CSn[3:0] active edge

to OSPI0_CLK rising edge

DDR

((0.475P(1)) +

(0.975M(2)R(4)) +

(0.04TD(5)) - 1)

((0.525P(1)) +

(1.025M(2)R(4)) +

(0.11TD(5)) + 1)

td(CLK-CSn)

Delay time, OSPI0_CLK rising edge to

OSPI0_CSn[3:0] inactive edge

DDR

((0.475P(1)) +

(0.975N(3)R(4)) -

(0.04TD(5)) - 1)

((0.525P(1)) +

(1.025N(3)R(4)) -

(0.11TD(5)) + 1)

td(CLK-D)

Delay time, OSPI0_CLK active edge to

OSPI0_D[7:0] transition

DDR

(6)

(1)

P = OSPI0_CLK cycle time = SCLK period in ns

(2)

M = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(3)

N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(4)

R = refclk cycle time in ns

(5)

TD = PHY_CONFIG_TX_DLL_DELAY_FLD

(6)

Minimum and maximum delay times for OSPI0_D[7:0] outputs are not defined when Data Training is used to find the optimum data

valid window.

OSPI_CLK

OSPI_TIMING_01

OSPI_CSn

OSPI_D[i:0]

Figure 7-80. OSPI0 Switching Characteristics – PHY DDR Data Training

AM2434, AM2432, AM2431

SPRSP65D – APRIL 2021 – REVISED AUGUST 2022

www.ti.com

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