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7.10.5.14.1.2 OSPI0 Without Data Training

Note

Timing parameters defined in this section are only applicable when data training is not implemented

and DLL delays are configured as described in Table 7-96 and Table 7-99.

7.10.5.14.1.2.1 OSPI0 PHY SDR Timing

Table 7-96 defines DLL delays required for OSPI0 PHY SDR Mode. Table 7-97, Figure 7-81, Figure 7-82, Table

7-98, and Figure 7-83 present timing requirements and switching characteristics for OSPI0 PHY SDR Mode.

Table 7-96. OSPI0 DLL Delay Mapping for PHY SDR Timing Modes

MODE

OSPI_PHY_CONFIGURATION_REG BIT FIELD

DELAY VALUE

Transmit

All modes

PHY_CONFIG_TX_DLL_DELAY_FLD,

0x0

Receive

All modes

PHY_CONFIG_RX_DLL_DELAY_FLD

0x0

Table 7-97. OSPI0 Timing Requirements – PHY SDR Mode

see Figure 7-81 and Figure 7-82

NO.

MODE

MIN

MAX

UNIT

O19

tsu(D-CLK)

Setup time, OSPI0_D[7:0] valid before

active OSPI0_CLK edge

1.8V, SDR with Internal PHY Loopback

-2.19

3.3V, SDR with Internal PHY Loopback

-1.71

O20

th(CLK-D)

Hold time, OSPI0_D[7:0] valid after active

OSPI0_CLK edge

1.8V, SDR with Internal PHY Loopback

7.62

3.3V, SDR with Internal PHY Loopback

8.1

O21

tsu(D-LBCLK)

Setup time, OSPI0_D[7:0] valid before

active OSPI0_DQS edge

1.8V, SDR with External Board Loopback

-3.1

3.3V, SDR with External Board Loopback

-3.47

O22

th(LBCLK-D)

Hold time, OSPI0_D[7:0] valid after active

OSPI0_DQS edge

1.8V, SDR with External Board Loopback

3.31

3.3V, SDR with External Board Loopback

4.33

OSPI_CLK

OSPI_D[i:0]

OSPI_TIMING_05

O 9

O20

Figure 7-81. OSPI0 Timing Requirements – PHY SDR with Internal PHY Loopback

OSPI_DQS

OSPI_TIMING_06

O21

O 2

OSPI_D[i:0]

Figure 7-82. OSPI0 Timing Requirements – PHY SDR with External Board Loopback

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AM2434, AM2432, AM2431

SPRSP65D – APRIL 2021 – REVISED AUGUST 2022

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