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7.10.5.14.1.2.2 OSPI0 PHY DDR Timing

Table 7-99 defines DLL delays required for OSPI0 PHY DDR Mode. Table 7-100, Figure 7-84, Table 7-101, and

Figure 7-85 present timing requirements and switching characteristics for OSPI0 PHY DDR Mode.

Table 7-99. OSPI0 DLL Delay Mapping for PHY DDR Timing Modes

MODE

OSPI_PHY_CONFIGURATION_REG BIT FIELD

DELAY VALUE

Transmit

1.8V

PHY_CONFIG_TX_DLL_DELAY_FLD

0x3E

3.3V

PHY_CONFIG_TX_DLL_DELAY_FLD

0x3B

Receive

1.8V, DQS

PHY_CONFIG_RX_DLL_DELAY_FLD

0x15

3.3V, DQS

PHY_CONFIG_RX_DLL_DELAY_FLD

0x3A

All other modes

PHY_CONFIG_RX_DLL_DELAY_FLD

0x0

Table 7-100. OSPI0 Timing Requirements – PHY DDR Mode

see Figure 7-84

NO.

MODE

MIN

MAX

UNIT

O15

tsu(D-LBCLK)

Setup time, OSPI0_D[7:0] valid before

active OSPI0_DQS edge

1.8V, DDR with External Board Loopback

0.53

1.8V, DDR with DQS

-0.46

3.3V, DDR with External Board Loopback

1.23

3.3V, DDR with DQS

-0.66

O16

th(LBCLK-D)

Hold time, OSPI0_D[7:0] valid after active

OSPI0_DQS edge

1.8V, DDR with External Board Loopback

1.24(1)

1.8V, DDR with DQS

3.59

3.3V, DDR with External Board Loopback

1.44(1)

3.3V, DDR with DQS

7.92

(1)

This Hold time requirement is larger than the Hold time provided by a typical OSPI/QSPI/SPI device. Therefore, the trace length

between the SoC and attached OSPI/QSPI/SPI device must be sufficiently long enough to ensure that the Hold time is met at the SoC.

The length of the SoC's external loopback clock (OSPI0_LBCLKO to OSPI0_DQS) may need to be shortened to compensate.

OSPI_DQS

O16

O15

OSPI_TIMING_04

OSPI_D[i:0]

O16

O15

Figure 7-84. OSPI0 Timing Requirements – PHY DDR with External Board Loopback or DQS

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AM2434, AM2432, AM2431

SPRSP65D – APRIL 2021 – REVISED AUGUST 2022

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