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7.10.5.14.2.2 OSPI0 Tap DDR Timing

Table 7-104, Figure 7-88, Table 7-105, and Figure 7-89 present timing requirements and switching

characteristics for OSPI0 Tap DDR Mode.

Table 7-104. OSPI0 Timing Requirements – Tap DDR Mode

see Figure 7-88

NO.

MODE

MIN

MAX

UNIT

O13

tsu(D-CLK)

Setup time, OSPI0_D[7:0] valid before

active OSPI0_CLK edge

No Loopback

(12.04 -

(0.975T(1)R(2)))

O14

th(CLK-D)

Hold time, OSPI0_D[7:0] valid after active

OSPI0_CLK edge

No Loopback

(1.84 +

(0.975T(1)R(2)))

(1)

T = OSPI_RD_DATA_CAPTURE_REG[DELAY_FLD]

(2)

R = refclk cycle time in ns

OSPI_CLK

O14

O13

OSPI_TIMING_03

OSPI_D[i:0]

O14

O13

Figure 7-88. OSPI0 Timing Requirements – Tap DDR, No Loopback

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AM2434, AM2432, AM2431

SPRSP65D – APRIL 2021 – REVISED AUGUST 2022

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