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7.10.5.16 PRU_ICSSG

The device has integrated two identical Programmable Real-Time Unit Subsystem and Industrial Communication

Subsystems - Gigabit (PRU_ICSSG), PRU_ICSSG0 and PRU_ICSSG1. The programmable nature of the PRU

cores, along with their access to pins, events and all device resources, provides flexibility in implementing fast

real-time responses, specialized data handling operations, custom peripheral interfaces, and in offloading tasks

from the other processor cores in the device.

For more details about features and additional description information on the device PRU_ICSSG, see the

corresponding subsections within Signal Descriptions and Detailed Description sections.

Note

The PRU_ICSSG contains a second layer of multiplexing to enable additional functionality on the PRU

GPO and GPI signals. This internal wrapper multiplexing is described in the PRU_ICSSG chapter in

the device TRM.

7.10.5.16.1 PRU_ICSSG Programmable Real-Time Unit (PRU)

Note

The PRU_ICSSG PRU signals have different functionality depending on the mode of operation. The

signal naming in this section matches the naming used in the PRU Module Interface section in the

device TRM.

Table 7-106. PRU_ICSSG PRU Timing Conditions

PARAMETER

MIN

MAX

UNIT

INPUT CONDITIONS

SRI

Input slew rate

V/ns

OUTPUT CONDITIONS

Output load capacitance

7.10.5.16.1.1 PRU_ICSSG PRU Direct Output Mode Timing

Table 7-107. PRU_ICSSG PRU Switching Characteristics – Direct Output Mode

see Figure 7-90

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

PRDO1

tsk(GPO-GPO)

Skew, GPO to GPO

GPO[n:0]

PRDO1

PRU_TIMING_02

n in GPO[n:0] = 19.

Figure 7-90. PRU_ICSSG PRU Direct Output Timing

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AM2434, AM2432, AM2431

SPRSP65D – APRIL 2021 – REVISED AUGUST 2022

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