STM32F405 datasheet(115/204 Pages) STMICROELECTRONICS

115 / 204 page

DS8626 Rev 9

115/203

STM32F405xx, STM32F407xx

Electrical characteristics

All I/Os are CMOS and TTL compliant (no software configuration required). Their

characteristics cover more than the strict CMOS-technology or TTL parameters.

VHYS

FT, TTa and NRST I/O input

hysteresis

1.7 V ≤ VDD ≤ 3.6 V

10%VDD(3)

BOOT0 I/O input hysteresis

1.75 V ≤ VDD ≤ 3.6 V

-40 °C≤ TA ≤ 105 °C

0.1

1.7 V ≤ VDD ≤ 3.6 V

0 °C≤ TA ≤ 105 °C

Ilkg

I/O input leakage current (4)

VSS ≤ VIN ≤ VDD

±1

µA

I/O FT input leakage current (5)

VIN = 5 V

RPU

Weak pull-up

equivalent

resistor(6)

All pins

except for

PA10 and

PB12

(OTG_FS_ID,

OTG_HS_ID)

VIN = VSS

PA10 and

PB12

(OTG_FS_ID,

OTG_HS_ID)

-7

RPD

Weak pull-down

equivalent

resistor(7)

All pins

except for

PA10 and

PB12

VIN = VDD

PA10 and

PB12

-7

CIO(8)

I/O pin

capacitance

-5

1. Guaranteed by design.

2. Tested in production.

3. With a minimum of 200 mV.

4. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins.Refer to Table 47: I/O

current injection susceptibility

5. To sustain a voltage higher than VDD + 0.3 V, the internal pull-up/pull-down resistors must be disabled. Leakage could be

higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 47: I/O current injection

susceptibility.

6. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS. This PMOS

contribution to the series resistance is minimum (~10% order)

7. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable NMOS. This NMOS

contribution to the series resistance is minimum (~10% order)

8. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization.

Table 48. I/O static characteristics (continued)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

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