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STM32F405 数据表(PDF) 116 Page - STMicroelectronics |
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STM32F405 数据表(HTML) 116 Page - STMicroelectronics |
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116 / 204 page  Electrical characteristics STM32F405xx, STM32F407xx 116/203 DS8626 Rev 9 Output driving current The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or source up to ±20 mA (with a relaxed VOL/VOH) except PC13, PC14 and PC15 which can sink or source up to ±3mA. When using the PC13 to PC15 GPIOs in output mode, the speed should not exceed 2 MHz with a maximum load of 30 pF. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 5.2. In particular: • The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 12). • The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 12). Output voltage levels Unless otherwise specified, the parameters given in Table 49 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. Table 49. Output voltage characteristics(1) 1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited: the speed should not exceed 2 MHz with a maximum load of 30 pF and these I/Os must not be used as a current source (e.g. to drive an LED). Symbol Parameter Conditions Min Max Unit VOL(2) 2. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. Output low level voltage CMOS port IIO = +8 mA 2.7 V < VDD < 3.6 V -0.4 V VOH(3) 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. Output high level voltage VDD–0.4 - VOL (2) Output low level voltage TTL port IIO =+ 8mA 2.7 V < VDD < 3.6 V -0.4 V VOH (3) Output high level voltage 2.4 - VOL(2)(4) 4. Guaranteed by characterization. Output low level voltage IIO = +20 mA 2.7 V < VDD < 3.6 V -1.3 V VOH(3)(4) Output high level voltage VDD–1.3 - VOL(2)(4) Output low level voltage IIO = +6 mA 2 V < VDD < 2.7 V -0.4 V VOH(3)(4) Output high level voltage VDD–0.4 - |
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