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STM32F405 数据表(PDF) 124 Page - STMicroelectronics |
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STM32F405 数据表(HTML) 124 Page - STMicroelectronics |
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124 / 204 page ![]() Electrical characteristics STM32F405xx, STM32F407xx 124/203 DS8626 Rev 9 Figure 39. SPI timing diagram - slave mode and CPHA = 0 Figure 40. SPI timing diagram - slave mode and CPHA = 1 MSv41658V1 NSS input CPHA=0 CPOL=0 CPHA=0 CPOL=1 MISO output MOSI input tsu(SI) th(SI) tw(SCKL) tw(SCKH) tc(SCK) tr(SCK) th(NSS) tdis(SO) tsu(NSS) ta(SO) tv(SO) Next bits IN Last bit OUT First bit IN First bit OUT Next bits OUT th(SO) tf(SCK) Last bit IN MSv41659V1 NSS input CPHA=1 CPOL=0 CPHA=1 CPOL=1 MISO output MOSI input tsu(SI) th(SI) tw(SCKL) tw(SCKH) tsu(NSS) tc(SCK) ta(SO) tv(SO) First bit OUT Next bits OUT Next bits IN Last bit OUT th(SO) tr(SCK) tf(SCK) th(NSS) tdis(SO) First bit IN Last bit IN |
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