STM32F405 datasheet(126/204 Pages) STMICROELECTRONICS

126 / 204 page

Electrical characteristics

STM32F405xx, STM32F407xx

126/203

DS8626 Rev 9

I2S interface characteristics

Unless otherwise specified, the parameters given in Table 56 for the i2S interface are

derived from tests performed under the ambient temperature, fPCLKx frequency and VDD

supply voltage conditions summarized in Table 14, with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

•

Capacitive load C = 30 pF

•

Measurement points are done at CMOS levels: 0.5 VDD

Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate

function characteristics (CK, SD, WS).

Note:

Refer to the I2S section of RM0090 reference manual for more details on the sampling

frequency (FS). fMCK, fCK, and DCK values reflect only the digital peripheral behavior. The

value of these parameters might be slightly impacted by the source clock accuracy. DCK

depends mainly on the value of ODD bit. The digital contribution leads to a minimum value

of I2SDIV / (2 x I2SDIV + ODD) and a maximum value of (I2SDIV + ODD) / (2 x I2SDIV +

ODD). FS maximum value is supported for each mode/condition.

Table 56. I2S dynamic characteristics(1)

Symbol

Parameter

Conditions

Min

Max

Unit

fMCK

I2S main clock output

256 x

256 x FS(2)

MHz

fCK

I2S clock frequency

Master data: 32 bits

64 x FS

MHz

Slave data: 32 bits

64 x FS

DCK

I2S clock frequency duty cycle Slave receiver

tv(WS)

WS valid time

Master mode

th(WS)

WS hold time

Master mode

tsu(WS)

WS setup time

Slave mode

th(WS)

WS hold time

Slave mode

tsu(SD_MR)

Data input setup time

Master receiver

7.5

tsu(SD_SR)

Slave receiver

th(SD_MR)

Data input hold time

Master receiver

th(SD_SR)

Slave receiver

tv(SD_ST)

th(SD_ST)

Data output valid time

Slave transmitter (after enable edge)

tv(SD_MT)

Master transmitter (after enable edge)

th(SD_MT)

Data output hold time

Master transmitter (after enable edge)

2.5

1. Guaranteed by characterization.

2. The maximum value of 256 x FS is 42 MHz (APB1 maximum frequency).

STM32F405 数据表(PDF) 126 Page - STMicroelectronics

STM32F405 数据表(HTML) 126 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载