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STM32F405 数据表(PDF) 130 Page - STMicroelectronics |
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STM32F405 数据表(HTML) 130 Page - STMicroelectronics |
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130 / 204 page ![]() Electrical characteristics STM32F405xx, STM32F407xx 130/203 DS8626 Rev 9 Figure 45. ULPI timing diagram Frequency (steady state) ±500 ppm FSTEADY 59.97 60 60.03 MHz Duty cycle (first transition) 8-bit ±10% DSTART_8BIT 40 50 60 % Duty cycle (steady state) ±500 ppm DSTEADY 49.975 50 50.025 % Time to reach the steady state frequency and duty cycle after the first transition TSTEADY -- 1.4 ms Clock startup time after the de-assertion of SuspendM Peripheral TSTART_DEV -- 5.6 ms Host TSTART_HOST -- - PHY preparation time after the first transition of the input clock TPREP -- - µs 1. Guaranteed by design. Table 62. ULPI timing Parameter Symbol Value(1) 1. VDD = 2.7 V to 3.6 V and TA = –40 to 85 °C. Unit Min. Max. Control in (ULPI_DIR) setup time tSC -2.0 ns Control in (ULPI_NXT) setup time - 1.5 Control in (ULPI_DIR, ULPI_NXT) hold time tHC 0- Data in setup time tSD -2.0 Data in hold time tHD 0- Control out (ULPI_STP) setup time and hold time tDC -9.2 Data out available from clock rising edge tDD -10.7 Table 61. USB HS clock timing parameters(1) Parameter Symbol Min Nominal Max Unit Clock Control In (ULPI_DIR, ULPI_NXT) data In (8-bit) Control out (ULPI_STP) data out (8-bit) tDD tDC tHD tSD tHC tSC ai17361c tDC |
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