STM32F405 datasheet(133/204 Pages) STMICROELECTRONICS

133 / 204 page

DS8626 Rev 9

133/203

STM32F405xx, STM32F407xx

Electrical characteristics

5.3.20

CAN (controller area network) interface

Refer to Section 5.3.16: I/O port characteristics for more details on the input/output alternate

function characteristics (CANTX and CANRX).

5.3.21

12-bit ADC characteristics

Unless otherwise specified, the parameters given in Table 67 are derived from tests

performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage

conditions summarized in Table 14.

Table 66. Dynamic characteristics: Ethernet MAC signals for MII(1)

1. Guaranteed by characterization.

Symbol

Parameter

Min

Typ

Max

Unit

tsu(RXD)

Receive data setup time

tih(RXD)

Receive data hold time

tsu(DV)

Data valid setup time

tih(DV)

Data valid hold time

tsu(ER)

Error setup time

tih(ER)

Error hold time

td(TXEN)

Transmit enable valid delay time

td(TXD)

Transmit data valid delay time

Table 67. ADC characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDDA

Power supply

1.8(1)

-3.6

VREF+

Positive reference voltage

1.8(1)(2)(3)

-VDDA

VREF−

Negative reference voltage

fADC

ADC clock frequency

VDDA = 1.8(1)(3) to

2.4 V

0.6

MHz

VDDA = 2.4 to 3.6 V(3)

0.6

MHz

fTRIG(4) External trigger frequency

fADC = 30 MHz,

12-bit resolution

1764

kHz

1/fADC

VAIN

Conversion voltage range(5)

0 (VSSAor VREF-

tied to ground)

-VREF+

RAIN(4)

External input impedance

See Equation 1 for

details

κΩ

RADC(4)(6) Sampling switch resistance

κΩ

CADC(4)

Internal sample and hold

capacitor

STM32F405 数据表(PDF) 133 Page - STMicroelectronics

STM32F405 数据表(HTML) 133 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载