ADE7169ASTF16 datasheet(121/140 Pages) AD

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Preliminary Technical Data

ADE7169F16

Rev. PrD | Page 121 of 140

possible.

Modes 1 and 3 Baud Rate =

× Timer 2 Overflow Rate

Therefore, when Timer 2 is used to generate baud rates, the

timer increments every two clock cycles rather than every core

machine cycle as before. It increments six times faster than

Timer 1, and, therefore, baud rates six times faster are possible.

Because Timer 2 has 16-bit autoreload capability, very low baud

rates are still possible.

Timer 2 is selected as the baud rate generator by setting the

TCLK and/or RCLK in T2CON. The baud rates for transmit

and receive can be simultaneously different. Setting RCLK

and/or TCLK puts Timer 2 into its baud rate generator mode as

shown in Figure 78.

In this case, the baud rate is given by the formula

Modes 1 and 3 Baud Rate =

()

[]

()

RCAP

core

65536

−

FCORE

TR2

CONTROL

TL2

(8 BITS)

TH2

(8 BITS)

RELOAD

EXEN2

CONTROL

T2EX

TRANSITION

DETECTOR

EXF 2

TIMER 2

INTERRUPT

NOTE: AVAILABILITY OF ADDITIONAL

EXTERNAL INTERRUPT

RCAP2L

RCAP2H

TIMER 2

OVERFLOW

RCLK

TCLK

CLOCK

SMOD

TIMER 1

OVERFLOW

C/ T2 = 0

C/ T2 = 1

Figure 78. Timer 2, UART Baud Rates

UART Timer Generated Baud Rates

The high integer dividers in a UART block mean that high

speed baud rates are not always possible. Also, generating baud

rates requires the exclusive use of a timer, rendering it unusable

for other applications when the UART is required. To address

this problem, the ADE7169F16 has a dedicated baud rate timer

(UART Timer) specifically for generating highly accurate baud

rates. UART Timer can be used instead of Timer 1 or Timer 2

for generating very accurate high speed UART baud rates

including 115200. UART Timer also allows a much wider range

of baud rates to be obtained. In fact, every desired bit rate from

12 bps to 393216 bps can be generated to within an error of

±0.8%. UART Timer also frees up the other three timers,

allowing them to be used for different applications. A block

diagram of UART Timer is shown in Figure 79.

⎟ (1 + SBAUDF/64)

UART Timer

Rx/Tx CLOCK

FCORE

UARTBAUDEN

Rx CLOCK

Tx CLOCK

TIMER 1/TIMER 2

Rx CLOCK

FRACTIONAL

DIVIDER

TIMER 1/TIMER 2

Tx CLOCK

⎟ 32

⎟ 2D IV+SBTH

Figure 79. UART Timer, UART Baud Rate

Two SFRs Enhanced Serial baud rate control SFR (SBAUDT,

0x9E) and UART Timer Fractional Divider SFR (SBAUDF,

0x9D) are used to control UART Timer. SBAUDT is the baud

rate control SFR; it sets up the integer divider (DIV) and the

extended divider (SBTH) for UART Timer.

ADE7169ASTF16 数据表(PDF) 121 Page - Analog Devices

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