ADE7169ASTF16 datasheet(117/140 Pages) AD

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Preliminary Technical Data

ADE7169F16

Rev. PrD | Page 117 of 140

In Modes 2 or 3, if SM2 is set, RI is not activated if the received ninth data bit in RB8 is

0. If SM2 is cleared, RI is set as soon as the byte of data is received.

0x9C

REN

Serial Port Receive Enable Bit.

Set by user software to enable serial port reception.

Cleared by user software to disable serial port reception.

0x9B

TB8

Serial Port Transmit (Bit 9).

The data loaded into TB8 is the ninth data bit transmitted in Modes 2 and 3.

0x9A

RB8

Serial Port Receiver Bit 9.

The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1, the stop

bit is latched into RB8.

0x99

Serial Port Transmit Interrupt Flag.

Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop

bit in Modes 1, 2, and 3.

TI must be cleared by user software.

0x98

Serial Port Receive Interrupt Flag.

Set by hardware at the end of the eighth bit in Mode 0, or halfway through the stop bit

in Modes 1, 2, and 3.

RI must be cleared by user software.

Table 117. Serial port Buffer SFR (SBUF, 0x99)

Bit

Location

Bit

Mnemonic

Default

Value

Description

7-0

SBUF

Serial port data buffer

Table 118. Enhanced Serial baud rate control SFR (SBAUDT, 0x9E)

Bit

Location

Bit

Mnemonic

Default

Value

Description

OWE

Overwrite Error. This bit is set when new data is received and RI=1. It indicates that

SBUF was not read before the next character was transferred in, causing the prior

SBUF data to be lost.

Frame Error. This bit is set when the received frame did not have a valid stop bit. This

bit is read only and updated every time a frame is received.

Break Error. This bit is set whenever the receive data line (Rx) is low for longer than a

full transmission frame, the time required for a start bit, 8 data bits, a parity bit and half

a stop bit. This bit is updated every time a frame is received.

4-3

SBTH1, SBTH0

Extended divider ratio for baud rate setting as shown in Table 120

2, 1, 0

DIV2, DIV1,

DIV0

Binary Divider

DIV2

DIV1

DIV0

Divide by 1. See Table 120.

Divide by 2. See Table 120.

Divide by 4. See Table 120.

Divide by 8. See Table 120.

Divide by 16. See Table 120.

Divide by 32. See Table 120.

Divide by 64. See Table 120.

Divide by 128. See Table 120.

ADE7169ASTF16 数据表(PDF) 117 Page - Analog Devices

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