AD9510SLASHPCB datasheet(32/60 Pages) AD

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AD9510

Rev. A | Page 32 of 60

OFF (LOW) (DEFAULT)

DIGITAL LOCK DETECT (ACTIVE HIGH)

N DIVIDER OUTPUT

DIGITAL LOCK DETECT (ACTIVE LOW)

R DIVIDER OUTPUT

ANALOG LOCK DETECT (N-CHANNEL OPEN DRAIN)

A COUNTER OUTPUT

PRESCALER OUTPUT (NCLK)

PFD UP PULSE

PFD DOWN PULSE

LOSS OF REFERENCE (ACTIVE HIGH)

TRI-STATE

ANALOG LOCK DETECT (P-CHANNEL OPEN DRAIN)

LOSS OF REFERENCE OR LOCK DETECT (ACTIVE HIGH)

LOSS OF REFERENCE OR LOCK DETECT (ACTIVE LOW)

LOSS OF REFERENCE (ACTIVE LOW)

PLL MUX CONTROL

08h <5:2>

SYNC DETECT ENABLE

58h <0>

SYNC

DETECT

GND

STATUS

Figure 37. STATUS Pin Circuit CLK1 Clock Input

PLL Analog Lock Detect

An analog lock detect (ALD) signal may be selected. When

ALD is selected, the signal at the STATUS pin is either an

open-drain P-channel (08h<5:2> = 1100) or an open-drain

N-channel (08h<5:2> = 0101b).

The analog lock detect signal is true (relative to the selected

mode) with brief false pulses. These false pulses get shorter as

the inputs to the PFD are nearer to coincidence and longer as

they are further from coincidence.

To extract a usable analog lock detect signal, an external RC

network is required to provide an analog filter with the

appropriate RC constant to allow for the discrimination of a

lock condition by an external voltage comparator. A 1 kΩ

resistor in parallel with a small capacitance usually fulfills this

requirement. However, some experimentation may be required

to get the desired operation.

The analog lock detect function may introduce some spurious

energy into the clock outputs. It is prudent to limit the use of

the ALD when the best possible jitter/phase noise performance

is required on the clock outputs.

Loss of Reference

The AD9510 PLL can warn of a loss-of-reference signal at

REFIN. The loss-of-reference monitor internally sets a flag

called LREF. Externally, this signal can be observed in several

ways on the STATUS pin, depending on the PLL MUX control

settings in Register 08h<5:2>. The LREF alone can be observed

as an active high signal by setting 08h<5:2> = <1010> or as an

active low signal by setting 08h<5:2> = <1111>.

The loss-of-reference circuit is clocked by the signal from the

VCO, which means that there must be a VCO signal present in

order to detect a loss of reference.

The digital lock detect (DLD) block of the AD9510 requires a

PLL reference signal to be present in order for the digital lock

detect output to be valid. It is possible to have a digital lock

detect indication (DLD = true) that remains true even after a

loss-of-reference signal. For this reason, the digital lock detect

signal alone cannot be relied upon if the reference has been lost.

There is a way to combine the DLD and the LREF into a single

signal at the STATUS pin. Set 08h<5:2> = <1101> to get a signal

that is the logical OR of the loss-of-lock (inverse of DLD) and

the loss-of-reference (LREF) active high. If an active low version

of this same signal is desired, set 08h<5:2> = <1110>.

The reference monitor is enabled only after the DLD signal has

been high for the number of PFD cycles set by the value in

07h<6:5>. This delay is measured in PFD cycles. The delay

ranges from 3 PFD cycles (default) to 24 PFD cycles. When the

reference goes away, LREF goes true and the charge pump goes

into tri-state.

User intervention is required to take the part out of this state.

First, 07h<2> = 0b must be written to disable the loss-of-

reference circuit, taking the charge pump out of tri-state and

causing LREF to go false. A second write of 07h<2> = 1 is

required to re-enable the loss-of-reference circuit.

PLL LOOP LOCKS

DLD GOES TRUE

LREF IS FALSE

CHECK FOR PRESENCE

OR REFERENCE.

LREF STAYS FALSE IF

REFERENCE IS DETECTED.

CHARGE PUMP

GOES INTO TRI-STATE.

LREF SET TRUE.

MISSING

REFERENCE

DETECTED

n PFD CYCLES WITH

DLD TRUE

(n SET BY 07h<6:5>)

WRITE 07h<2> = 0

LREF SET FALSE

CHARGE PUMP COMES

OUT OF TRI-STATE

WRITE 07h<2> = 1

LOR ENABLED

Figure 38. Loss of Reference Sequence of Events

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