| 数据搜索系统,热门电子元器件搜索 |
|
AD9510/PCB 数据表(PDF) 58 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
AD9510/PCB 数据表(HTML) 58 Page - Analog Devices |
|
58 / 60 page ![]() AD9510 Rev. A | Page 58 of 60 Because of the limitations of single-ended CMOS clocking, consider using differential outputs when driving high speed signals over long traces. The AD9510 offers both LVPECL and LVDS outputs, which are better suited for driving long traces where the inherent noise immunity of differential signaling provides superior performance for clocking converters. LVPECL CLOCK DISTRIBUTION The low voltage, positive emitter-coupled, logic (LVPECL) outputs of the AD9510 provide the lowest jitter clock signals available from the AD9510. The LVPECL outputs (because they are open emitter) require a dc termination to bias the output transistors. A simplified equivalent circuit in Figure 41 shows the LVPECL output stage. In most applications, a standard LVPECL far-end termination is recommended, as shown in Figure 56. The resistor network is designed to match the transmission line impedance (50 Ω) and the desired switching threshold (1.3 V). 3.3V LVPECL 50 Ω 50 Ω SINGLE-ENDED (NOT COUPLED) 3.3V 3.3V LVPECL 127 Ω 127 Ω 83 Ω 83 Ω VT = VCC – 1.3V Figure 56. LVPECL Far-End Termination 3.3V LVPECL DIFFERENTIAL (COUPLED) 3.3V LVPECL 100 Ω 0.1nF 0.1nF 200 Ω 200 Ω Figure 57. LVPECL with Parallel Transmission Line LVDS CLOCK DISTRIBUTION Low voltage differential signaling (LVDS) is a second differential output option for the AD9510. LVDS uses a current mode output stage with several user-selectable current levels. The normal value (default) for this current is 3.5 mA, which yields 350 mV output swing across a 100 Ω resistor. The LVDS outputs meet or exceed all ANSI/TIA/EIA-644 specifications. A recommended termination circuit for the LVDS outputs is shown in Figure 58. 3.3V LVDS 100 Ω DIFFERENTIAL (COUPLED) 3.3V LVDS 100 Ω Figure 58. LVDS Output Termination See Application Note AN-586 on the ADI website at www.analog.com for more information on LVDS. POWER AND GROUNDING CONSIDERATIONS AND POWER SUPPLY REJECTION Many applications seek high speed and performance under less than ideal operating conditions. In these application circuits, the implementation and construction of the PCB is as important as the circuit design. Proper RF techniques must be used for device selection, placement, and routing, as well as for power supply bypassing and grounding to ensure optimum performance. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |