AD9510SLASHPCB datasheet(1/60 Pages) AD

部件名	AD9510/PCB

功能描述	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

PDF	60 Pages

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制造商	AD [Analog Devices]

网页	http://www.analog.com

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1.2 GHz Clock Distribution IC, PLL Core,

Dividers, Delay Adjust, Eight Outputs

AD9510

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.461.3113

FEATURES

Low phase noise phase-locked loop core

Reference input frequencies to 250 MHz

Programmable dual-modulus prescaler

Programmable charge pump (CP) current

Separate CP supply (VCPS) extends tuning range

Two 1.6 GHz, differential clock inputs

8 programmable dividers, 1 to 32, all integers

Phase select for output-to-output coarse delay adjust

4 independent 1.2 GHz LVPECL outputs

Additive output jitter 225 fs rms

4 independent 800 MHz/250 MHz LVDS/CMOS clock outputs

Additive output jitter 275 fs rms

Fine delay adjust on 2 LVDS/CMOS outputs

Serial control port

Space-saving 64-lead LFCSP

APPLICATIONS

Low jitter, low phase noise clock distribution

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

High performance instrumentation

Broadband infrastructure

FUNCTIONAL BLOCK DIAGRAM

R DIVIDER

N DIVIDER

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

PLL

SETTINGS

CLK2

STATUS

CLK2B

PROGRAMMABLE

DIVIDERS AND

PHASE ADJUST

OUT7

OUT7B

LVDS/CMOS

/1, /2, /3... /31, /32

OUT6

OUT6B

LVDS/CMOS

/1, /2, /3... /31, /32

OUT0

OUT0B

LVPECL

/1, /2, /3... /31, /32

OUT1

OUT1B

LVPECL

/1, /2, /3... /31, /32

OUT2

OUT2B

LVPECL

/1, /2, /3... /31, /32

OUT3

OUT3B

LVPECL

/1, /2, /3... /31, /32

OUT4

OUT4B

LVDS/CMOS

/1, /2, /3... /31, /32

OUT5

OUT5B

LVDS/CMOS

/1, /2, /3... /31, /32

ΔT

CLK1

CLK1B

REFIN

REFINB

FUNCTION

SCLK

SDIO

SDO

CSB

SERIAL

CONTROL

PORT

CP

CPRSET

DISTRIBUTION

REF

SYNCB,

RESETB

PDB

RSET

AD9510

GND

VS

VCP

PLL

REF

Figure 1.

GENERAL DESCRIPTION

The AD9510 provides a multi-output clock distribution

function along with an on-chip PLL core. The design emphasizes

low jitter and phase noise to maximize data converter

performance. Other applications with demanding phase noise

and jitter requirements also benefit from this part.

The PLL section consists of a programmable reference divider

(R); a low noise phase frequency detector (PFD); a precision

charge pump (CP); and a programmable feedback divider (N).

By connecting an external VCXO or VCO to the CLK2/CLK2B

pins, frequencies up to 1.6 GHz may be synchronized to the

input reference.

There are eight independent clock outputs. Four outputs are

LVPECL (1.2 GHz), and four are selectable as either LVDS

(800 MHz) or CMOS (250 MHz) levels.

Each output has a programmable divider that may be bypassed

or set to divide by any integer up to 32. The phase of one clock

output relative to another clock output may be varied by means

of a divider phase select function that serves as a coarse timing

adjustment. Two of the LVDS/CMOS outputs feature

programmable delay elements with full-scale ranges up to 10 ns

of delay. This fine tuning delay block has 5-bit resolution, giving

32 possible delays from which to choose for each full-scale

setting.

The AD9510 is ideally suited for data converter clocking

applications where maximum converter performance is

achieved by encode signals with subpicosecond jitter.

The AD9510 is available in a 64-lead LFCSP and can be

operated from a single 3.3 V supply. An external VCO, which

requires an extended voltage range, can be accommodated

by connecting the charge pump supply (VCP) to 5.5 V. The

temperature range is −40°C to +85°C.

类似零件编号 - AD9510/PCB

制造商	部件名	数据表	功能描述
Analog Devices	AD9510	1Mb / 56P	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs 9/2016-Rev. B to Rev. C
	AD9510	886Kb / 56P	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs REV. B
	AD9510	1Mb / 56P	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs 9/2016-Rev. B to Rev. C

More results

类似说明 - AD9510/PCB

制造商	部件名	数据表	功能描述
Analog Devices	AD9511	1Mb / 60P	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs 6/05-Rev. 0 to Rev. A
	AD9514	633Kb / 28P	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs 7/05-Revision 0
	AD9515	656Kb / 28P	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs 7/05-Revision 0
	AD9512BCPZ	967Kb / 48P	1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs REV. A
	AD9510	886Kb / 56P	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs REV. B
	AD9511	1Mb / 60P	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs REV. A
	AD9514	634Kb / 28P	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs REV. 0
	AD9515	469Kb / 28P	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs REV. A
	AD9510	1Mb / 56P	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs 9/2016-Rev. B to Rev. C
	AD9515	407Kb / 28P	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs Rev. B

More results

AD9510/PCB 数据表(PDF) 1 Page - Analog Devices

AD9510/PCB 数据表(HTML) 1 Page - Analog Devices

类似零件编号 - AD9510/PCB

类似说明 - AD9510/PCB

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AD9510/PCB 数据表(PDF) 1 Page - Analog Devices

AD9510/PCB 数据表(HTML) 1 Page - Analog Devices

类似零件编号 - AD9510/PCB

类似说明 - AD9510/PCB

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