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AD9510/PCB 数据表(PDF) 51 Page - Analog Devices

部件名 AD9510/PCB
功能描述  1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs
PDF  60 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD9510/PCB 数据表(HTML) 51 Page - Analog Devices

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AD9510
Rev. A | Page 51 of 60
Reg.
Addr.
(Hex) Bit(s) Name
Description
0A
<4:2> Prescaler Value
(P/P+1)
<4>
<3>
<2>
Mode
Prescaler Mode
0
0
0
FD
Divide by 1
0
0
1
FD
Divide by 2
0
1
0
DM
2/3
0
1
1
DM
4/5
1
0
0
DM
8/9
1
0
1
DM
16/17
1
1
0
DM
32/33
1
1
1
FD
Divide by 3
DM = Dual Modulus, FD = Fixed Divide.
0A
<5>
Not Used
0A
<6>
B Counter Bypass
Only valid when operating the prescaler in fixed divide (FD) mode. When this bit is set, the B counter is
divided by 1. This allows the prescaler setting to determine the divide for the N divider.
0A
<7>
Not Used
0B
<5:0> 14-Bit Reference
Counter, MSBs
R Divider (MSB) <13:8>
0C
<7:0> 14-Bit Reference
Counter, R LSBs
R Divider (MSB) <7:0>
0D
<1:0> Antibacklash Pulse
Width
<1>
<0>
Antibacklash Pulse Width (ns)
0
0
1.3 (Default)
0
1
2.9
1
0
6.0
1
1
1.3
0D
<4:2>
Not Used
0D
<5>
Digital Lock Detect
Window
<5>
Digital Lock Detect Window (ns)
Digital Lock Detect Loss-of-Lock Threshold (ns)
0 (Default)
9.5
15
1
3.5
7
Digital Lock Detect
Window
If the time difference of the rising edges at the inputs to the PFD are less than the lock detect window
time, the digital lock detect flag is set. The flag remains set until the time difference is greater than the
loss-of-lock threshold.
0D
<6>
Lock Detect
Disable
0 = Normal Lock Detect Operation (Default)
1 = Disable Lock Detect
0D
<7>
Not Used
Unused
0E-33
Not Used
Fine Delay Adjust
<0>
Delay Control
Delay Block Control Bit
34
OUT5
Bypasses Delay Block and Powers It Down (Default = 1b)
(38)
(OUT6)
34
<7:1>
Not Used
(38)
<2:0> Ramp Current
35
OUT5
The slowest ramp (200 μA) sets the longest full scale of approximately 10 ns.



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