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AD9510

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STATUS PIN

Table 10.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OUTPUT CHARACTERISTICS

When selected as a digital output (CMOS); there are other modes

in which the STATUS pin is not CMOS digital output. See Figure 37.

Output Voltage High (VOH)

2.7

Output Voltage Low (VOL)

0.4

MAXIMUM TOGGLE RATE

100

MHz

Applies when PLL mux is set to any divider or counter output,

or PFD up/down pulse. Also applies in analog lock detect mode.

Usually debug mode only. Beware that spurs may couple

to output when this pin is toggling.

ANALOG LOCK DETECT

Capacitance

On-chip capacitance; used to calculate RC time

constant for analog lock detect readback. Use a pull-up resistor.

POWER

Table 11.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER-UP DEFAULT MODE POWER DISSIPATION

550

600

Power-up default state; does not include power

dissipated in output load resistors. No clock.

Power Dissipation

1.1

All outputs on. Four LVPECL outputs @ 800 MHz,

4 LVDS out @ 800 MHz. Does not include power

dissipated in external resistors.

Power Dissipation

1.3

All outputs on. Four LVPECL outputs @ 800 MHz,

4 CMOS out@ 62 MHz (5 pF load). Does not include

power dissipated in external resistors.

Power Dissipation

1.5

All outputs on. Four LVPECL outputs @ 800 MHz,

4 CMOS out @ 125 MHz (5 pF load). Does not include

power dissipated in external resistors.

Full Sleep Power-Down

Maximum sleep is entered by setting 0Ah<1:0> = 01b

and 58h<4> = 1b. This powers off the PLL BG and the

distribution BG references. Does not include power

dissipated in terminations.

Power-Down (PDB)

Set the FUNCTION pin for PDB operation by setting

58h<6:5> = 11b. Pull PDB low. Does not include

power dissipated in terminations.

POWER DELTA

CLK1, CLK2 Power-Down

Divider, DIV 2 − 32 to Bypass

For each divider.

LVPECL Output Power-Down (PD2, PD3)

For each output. Does not include dissipation

in termination (PD2 only).

LVDS Output Power-Down

110

For each output.

CMOS Output Power-Down (Static)

For each output. Static (no clock).

CMOS Output Power-Down (Dynamic)

115

150

190

For each CMOS output, single-ended.

Clocking at 62 MHz with 5 pF load.

CMOS Output Power-Down (Dynamic)

125

165

210

For each CMOS output, single-ended.

Clocking at 125 MHz with 5 pF load.

Delay Block Bypass

Versus delay block operation at 1 ns fs

with maximum delay; output clocking at 25 MHz.

PLL Section Power-Down

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