AD9510SLASHPCB datasheet(40/60 Pages) AD

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AD9510

Rev. A | Page 40 of 60

3.5mA

OUT

OUTB

Figure 42. LVDS Output Simplified Equivalent Circuit

POWER-DOWN MODES

Chip Power-Down or Sleep Mode—PDB

The PDB chip power-down turns off most of the functions

and currents in the AD9510. When the PDB mode is enabled, a

chip power-down is activated by taking the FUNCTION pin to

a logic low level. The chip remains in this power-down state

until PDB is brought back to logic high. When woken up, the

AD9510 returns to the settings programmed into its registers

prior to the power-down, unless the registers are changed by

new programming while the PDB mode is active.

The PDB power-down mode shuts down the currents on the

chip, except the bias current necessary to maintain the LVPECL

outputs in a safe shutdown mode. This is needed to protect the

LVPECL output circuitry from damage that could be caused by

certain termination and load configurations when tri-stated.

Because this is not a complete power-down, it can be called

sleep mode.

When the AD9510 is in a PDB power-down or sleep mode, the

chip is in the following state:

•

The PLL is off (asynchronous power-down).

•

All clocks and sync circuits are off.

•

All dividers are off.

•

All LVDS/CMOS outputs are off.

•

All LVPECL outputs are in safe off mode.

•

The serial control port is active, and the chip responds to

commands.

If the AD9510 clock outputs must be synchronized to each

other, a SYNC (see the Single-Chip Synchronization section) is

required upon exiting power-down mode.

PLL Power-Down

The PLL section of the AD9510 can be selectively powered

down. There are three PLL power-down modes, set by the

values in Register 0Ah<1:0>, as shown in Table 19.

Table 19. Register 0Ah: PLL Power-Down

<1>

<0>

Mode

Normal Operation

Asynchronous Power-Down

Normal Operation

Synchronous Power-Down

In asynchronous power-down mode, the device powers down as

soon as the registers are updated.

In synchronous power-down mode, the PLL power-down is

gated by the charge pump to prevent unwanted frequency

jumps. The device goes into power-down on the occurrence of

the next charge pump event after the registers are updated.

Distribution Power-Down

The distribution section can be powered down by writing to

section. If the LVPECL power-down mode is normal operation

<00>, it is possible for a low impedance load on that LVPECL

output to draw significant current during this power-down. If

the LVPECL power-down mode is set to <11>, the LVPECL

output is not protected from reverse bias and can be damaged

under certain termination conditions.

When combined with the PLL power-down, this mode results in

the lowest possible power-down current for the AD9510.

Individual Clock Output Power-Down

Any of the eight clock distribution outputs may be powered

down individually by writing to the appropriate registers via the

SCP. The register map details the individual power-down

settings for each output. The LVDS/CMOS outputs may be

powered down, regardless of their output load configuration.

The LVPECL outputs have multiple power-down modes (see

and Register Address 3F in Table 24). These give some

flexibility in dealing with various output termination

conditions. When the mode is set to <10>, the LVPECL output

is protected from reverse bias to 2 VBE + 1 V. If the mode is set

to <11>, the LVPECL output is not protected from reverse bias

and can be damaged under certain termination conditions. This

setting also affects the operation when the distribution block is

powered down with Register 58h<3> = 1b (see the Distribution

Power-Down section).

Individual Circuit Block Power-Down

Many of the AD9510 circuit blocks (CLK1, CLK2, REFIN, and

so on) can be powered down individually. This gives flexibility

in configuring the part for power savings whenever certain chip

functions are not needed.

AD9510/PCB 数据表(PDF) 40 Page - Analog Devices

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