AD9510SLASHPCB datasheet(54/60 Pages) AD

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AD9510

Rev. A | Page 54 of 60

Reg.

Addr.

(Hex) Bit(s) Name

Description

<0>

Clock Select

0: CLK2 Drives Distribution Section

1: CLK1 Drives Distribution Section (Default)

<1>

CLK1 Power-Down 1 = CLK1 Input Is Powered Down (Default = 0b)

<2>

CLK2 Power-Down 1 = CLK2 Input Is Powered Down (Default = 0b)

<3>

Prescaler Clock

Power-Down

1 = Shut Down Clock Signal to PLL Prescaler (Default = 0b)

<4>

REFIN Power-Down 1 = Power-Down REFIN (Default = 0b)

<5>

All Clock Inputs

Power-Down

1 = Power-Down CLK1 and CLK2 Inputs and Associated Bias and Internal Clock Tree;

(Default = 0b)

<7:6>

Not Used

<7:0>

Not Used

<7:0>

Not Used

<3:0> Divider High

Number of Clock Cycles Divider Output Stays High

OUT0

(4A)

(OUT1)

(4C)

(OUT2)

(4E)

(OUT3)

(50)

(OUT4)

(52)

(OUT5)

(54)

(OUT6)

(56)

(OUT7)

<7:4> Divider Low

Number of Clock Cycles Divider Output Stays Low

OUT0

(4A)

(OUT1)

(4C)

(OUT2)

(4E)

(OUT3)

(50)

(OUT4)

(52)

(OUT5)

(54)

(OUT6)

(56)

(OUT7)

<3:0> Phase Offset

Phase Offset (Default = 0000b)

OUT0

(4B)

(OUT1)

(4D)

(OUT2)

(4F)

(OUT3)

(51)

(OUT4)

(53)

(OUT5)

(55)

(OUT6)

(57)

(OUT7)

<4>

Start

Selects Start High or Start Low

(Default = 0b)

OUT0

(4B)

(OUT1)

(4D)

(OUT2)

(4F)

(OUT3)

(51)

(OUT4)

(53)

(OUT5)

(55)

(OUT6)

(57)

(OUT7)

AD9510/PCB 数据表(PDF) 54 Page - Analog Devices

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AD9510/PCB 数据表(PDF) 54 Page - Analog Devices

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