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AD9510/PCB 数据表(PDF) 17 Page - Analog Devices |
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AD9510/PCB 数据表(HTML) 17 Page - Analog Devices |
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17 / 60 page ![]() AD9510 Rev. A | Page 17 of 60 TIMING DIAGRAMS CLK1 tCMOS tCLK1 tLVDS tPECL Figure 2. CLK1/CLK1B to Clock Output Timing, DIV = 1 Mode DIFFERENTIAL LVPECL 80% 20% tRP tFP Figure 3. LVPECL Timing, Differential DIFFERENTIAL LVDS 80% 20% tRL tFL Figure 4. LVDS Timing, Differential SINGLE-ENDED CMOS 3pF LOAD 80% 20% tRC tFC Figure 5. CMOS Timing, Single-Ended, 3 pF Load |
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