ST92F124 datasheet(228/429 Pages) STMICROELECTRONICS

228 / 429 page

228/429

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)

INTERRUPT VECTOR REGISTER (S_IVR)

R244 - Read/Write

Reset value: undefined

Bit 7:3 = V[7:3]: SCI Interrupt Vector Base Ad-

dress.

User programmable interrupt vector bits for trans-

mitter and receiver.

Bit 2:1 = EV[2:1]: Encoded Interrupt Source.

Both bits EV2 and EV1 are read only and set by

hardware according to the interrupt source.

Bit 0 = D0: This bit is forced by hardware to 0.

ADDRESS/DATA COMPARE REGISTER (ACR)

R245 - Read/Write

Reset value: undefined

Bit 7:0 = AC[7:0]: Address/Compare Character.

With either 9th bit address mode, address after

break mode, or character search, the received ad-

dress will be compared to the value stored in this

ter content, the Receiver Address Pending bit

(RXAP in the S_ISR register) is set. After the

RXAP bit is set in an addressed mode, all received

data words will be transferred to the Receiver Buff-

er Register.

EV2

EV1

EV2 EV1

Interrupt source

Receiver Error (Overrun, Framing, Parity)

Break Detect or Address Match

Received Data Pending/Receiver DMA

End of Block

Transmitter buffer or shift register empty

transmitter DMA End of Block

AC7

AC6

AC5

AC4

AC3

AC2

AC1

AC0

ST92F124 数据表(PDF) 228 Page - STMicroelectronics

ST92F124 数据表(HTML) 228 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载