ST92F124 datasheet(232/429 Pages) STMICROELECTRONICS

232 / 429 page

232/429

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (SCI-M)

MULTIPROTOCOL SERIAL COMMUNICATIONS INTERFACE (Cont’d)

INTERRUPT/DMA PRIORITY REGISTER (IDPR)

R249 - Read/Write

Reset value: undefined

Bit 7 = AMEN: Address Mode Enable.

This bit, together with the AM bit (in the CHCR reg-

ister), decodes the desired addressing/9th data

bit/character match operation.

In Address mode the SCI monitors the input serial

data until its address is detected

Note: Upon reception of address, the RXAP bit (in

the Interrupt Status Register) is set and an inter-

rupt cycle can begin. The address character will

not be transferred into the Receiver Buffer Regis-

ter but all data following the matched SCI address

and preceding the next address word will be trans-

ferred to the Receiver Buffer Register and the

proper interrupts updated. If the address does not

match, all data following this unmatched address

will not be transferred to the Receiver Buffer Reg-

ister.

In any of the cases the RXAP bit must be reset by

software before the next word is transferred into

the Buffer Register.

When AMEN is reset and AM is set, a useful char-

acter search function is performed. This allows the

SCI to generate an interrupt whenever a specific

character is encountered (e.g. Carriage Return).

Bit 6 = SB: Set Break.

0: Stop the break transmission after minimum

break length.

1: Transmit a break following the transmission of all

data in the Transmitter Shift Register and the

Buffer Register.

Note: The break will be a low level on the transmit-

ter data output for at least one complete word for-

mat. If software does not reset SB before the min-

imum break length has finished, the break condi-

tion will continue until software resets SB. The SCI

terminates the break condition with a high level on

the transmitter data output for one transmission

clock period.

Bit 5 = SA: Set Address.

If an address/9th data bit mode is selected, SA val-

ue will be loaded for transmission into the Shift

load.

0: Indicate it is not an address word.

1: Indicate an address word.

Note: Proper procedure would be, when the

Transmitter Buffer Register is empty, to load the

value of SA and then load the data into the Trans-

mitter Buffer Register.

Bit 4 = RXD: Receiver DMA Mask.

This bit is reset by hardware when the transaction

counter value decrements to zero. At that time a

receiver End of Block interrupt can occur.

0: Disable Receiver DMA request (the RXDP bit in

the S_ISR register can request an interrupt).

1: Enable Receiver DMA request (the RXDP bit in

the S_ISR register can request a DMA transfer).

Bit 3 = TXD: Transmitter DMA Mask.

This bit is reset by hardware when the transaction

counter value decrements to zero. At that time a

transmitter End Of Block interrupt can occur.

0: Disable Transmitter DMA request (TXBEM or

TXSEM bits in S_ISR can request an interrupt).

1: Enable Transmitter DMA request (TXBEM or

TXSEM bits in S_ISR can request a DMA trans-

fer).

Bit 2:0 = PRL[2:0]: SCI Interrupt/DMA Priority bits.

The

priority

for

the

SCI

encoded

with

(PRL2,PRL1,PRL0). Priority level 0 is the highest,

while level 7 represents no priority.

When the user has defined a priority level for the

SCI, priorities within the SCI are hardware defined.

These SCI internal priorities are:

AMEN

RXD

TXD

PRL2

PRL1

PRL0

AMEN

Address interrupt if 9th data bit = 1

Address interrupt if character match

and 9th data bit =1

Address interrupt if character match

with word immediately following Break

Receiver DMA request

highest priority

Transmitter DMA request

Receiver interrupt

Transmitter interrupt

lowest priority

ST92F124 数据表(PDF) 232 Page - STMicroelectronics

ST92F124 数据表(HTML) 232 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载