ST92F124 datasheet(275/429 Pages) STMICROELECTRONICS

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I2C BUS INTERFACE

I2C BUS INTERFACE (Cont’d)

– Address byte successfully transmitted in Mas-

ter mode.

(I2CSR1.EVF = 1 and I2CSR2.ADDTX=1)

Bit 6 = ADD10 10-bit addressing in Master mode.

This bit is set when the master has sent the first

byte in 10-bit address mode. An interrupt is gener-

ated if ITE=1.

It is cleared by software reading I2CSR1 register

followed by a write in the I2CDR register of the

second address byte. It is also cleared by hard-

ware when peripheral is disabled (I2CCR.PE=0)

or when the STOPF bit is set.

0: No ADD10 event occurred.

1: Master has sent first address byte (header).

Bit 5 = TRA Transmitter/ Receiver.

When BTF flag of this register is set and also

TRA=1, then a data byte has to be transmitted. It is

cleared automatically when BTF is cleared. It is

also cleared by hardware after the STOPF flag of

I2CSR2 register is set, loss of bus arbitration

(ARLO flag of I2CSR2 register is set) or when the

interface is disabled (I2CCR.PE=0).

0: A data byte is received (if I2CSR1.BTF=1)

1: A data byte can be transmitted (if

I2CSR1.BTF=1)

Bit 4 = BUSY Bus Busy.

It indicates a communication in progress on the

bus. The detection of the communications is al-

ways active (even if the peripheral is disabled).

This bit is set by hardware on detection of a Start

condition and cleared by hardware on detection of

a Stop condition. This information is still updated

when the interface is disabled (I2CCR.PE=0).

0: No communication on the bus

1: Communication ongoing on the bus

Bit 3 = BTF Byte Transfer Finished.

This bit is set by hardware as soon as a byte is cor-

rectly received or before the transmission of a data

byte with interrupt generation if ITE=1. It is cleared

by software reading I2CSR1 register followed by a

read or write of I2CDR register or when DMA is

complete. It is also cleared by hardware when the

interface is disabled (I2CCR.PE=0).

– Following a byte transmission, this bit is set after

reception of the acknowledge clock pulse. BTF is

cleared by reading I2CSR1 register followed by

writing the next byte in I2CDR register or when

DMA is complete.

– Following a byte reception, this bit is set after

transmission of the acknowledge clock pulse if

ACK=1. BTF is cleared by reading I2CSR1 reg-

ister followed by reading the byte from I2CDR

The SCL line is held low while I2CSR1.BTF=1.

0: Byte transfer not done

1: Byte transfer succeeded

Bit 2 = ADSL Address matched (Slave mode).

This bit is set by hardware if the received slave ad-

dress matches the I2COAR1/I2COAR2 register

content or a General Call address. An interrupt is

generated if ITE=1. It is cleared by software

reading I2CSR1 register or by hardware when the

interface is disabled (I2CCR.PE=0). The SCL line

is held low while ADSL=1.

0: Address mismatched or not received

1: Received address matched

Bit 1 = M/SL Master/Slave.

This bit is set by hardware as soon as the interface

is in Master mode (Start condition generated on

the lines after the I2CCR.START bit is set). It is

cleared by hardware after detecting a Stop condi-

tion on the bus or a loss of arbitration (ARLO=1). It

is also cleared when the interface is disabled

(I2CCR.PE=0).

0: Slave mode

1: Master mode

Bit 0 = SB Start Bit (Master mode).

This bit is set by hardware as soon as the Start

condition is generated (following a write of

START=1 if the bus is free). An interrupt is gener-

ated if ITE=1. It is cleared by software reading

I2CSR1 register followed by writing the address

byte in I2CDR register. It is also cleared by hard-

ware

when

the

interface

disabled

(I2CCR.PE=0).

The SCL line is held low while SB=1.

0: No Start condition

1: Start condition generated

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