ST92F124 datasheet(272/429 Pages) STMICROELECTRONICS

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I2C BUS INTERFACE

I2C BUS INTERFACE (Cont’d)

10.8.6.1 DMA between Peripheral and Register

File

If the DMA transaction is made between the pe-

ripheral and the Register File, one register is

required to hold the DMA Address and one to hold

the DMA transaction counter.

These two registers must be located in the Regis-

ter File:

– the DMA Address Register in the even ad-

dressed register,

– the DMA Transaction Counter in the following

They are pointed to by the DMA Transaction

Counter Pointer Register (I2CRDC register in re-

ceiving, I2CTDC register in transmitting) located in

the peripheral register page.

In order to select the DMA transaction with the

receiving mode or I2CTDC.RF/MEM in transmit-

ting mode must be set.

The transaction Counter Register must be initial-

ized with the number of DMA transfers to perform

and will be decremented after each transaction.

The DMA Address Register must be initialized with

the starting address of the DMA table in the Regis-

ter File, and it is increased after each transaction.

These two registers must be located between ad-

dresses 00h and DFh of the Register File.

When the DMA occurs between Peripheral and

sion) and the I2CRDAP one (in reception) are not

used.

10.8.6.2 DMA between Peripheral and Memory

Space

If the DMA transaction is made between the pe-

ripheral and Memory, a register pair is required to

hold the DMA Address and another register pair to

hold the DMA Transaction counter. These two

pairs of registers must be located in the Register

File. The DMA Address pair is pointed to by the

DMA Address Pointer Register (I2CRDAP register

in reception, I2CTDAP register in transmission) lo-

cated in the peripheral register page; the DMA

Transaction Counter pair is pointed to by the DMA

Transaction Counter Pointer Register (I2CRDC

sion) located in the peripheral register page.

In order to select the DMA transaction with the

Memory Space, the control bit I2CRDC.RF/MEM

in receiving mode or I2CTDC.RF/MEM in transmit-

ting mode must be reset.

The Transaction Counter registers pair must be in-

itialized with the number of DMA transfers to per-

form and will be decremented after each transac-

tion. The DMA Address register pair must be ini-

tialized with the starting address of the DMA table

in the Memory Space, and it is increased after

each transaction. These two register pairs must be

located between addresses 00h and DFh of the

10.8.6.3 DMA in Master Receive

To correctly manage the reception of the last byte

when the DMA in Master Receive mode is used,

the following sequence of operations must be per-

formed:

1. The number of data bytes to be received must

be set to the effective number of bytes minus

one byte.

2. When the Receiving End Of Block condition

occurs, the I2CCR.STOP bit must be set and

the I2CCR.ACK bit must be reset.

The last byte of the reception sequence can be re-

ceived either using interrupts/polling or using

DMA. If the user wants to receive the last byte us-

ing DMA, the number of bytes to be received must

be set to 1, and the DMA in reception must be re-

enabled (IMR.RXDM bit set) to receive the last

byte. Moreover the Receiving End Of Block inter-

rupt service routine must be designed to recognize

and manage the two different End Of Block situa-

tions (after the first sequence of data bytes and af-

ter the last data byte).

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