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ST92F124 数据表(PDF) 269 Page - STMicroelectronics |
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ST92F124 数据表(HTML) 269 Page - STMicroelectronics |
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269 / 429 page  269/429 I2C BUS INTERFACE EV5: EVF=1, SB=1, cleared by reading SR1 register followed by writing DR register. EV6: EVF=1, ADDTX=1, cleared by reading SR1 register followed by writing CR register (for example PE=1). EV7: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register or when DMA is complete. EV8: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register or when DMA is complete. EV9: EVF=1, ADD10=1, cleared by reading SR1 register followed by writing DR register. Figure 129. Event Flags and Interrupt Generation ADSL SB AF STOPF ARLO BERR ADD10 ADDTX ITE IERRM IERRP ERROR INTERRUPT REQUEST BTF=1 & TRA=0 Receiving DMA ITE IRXM IRXP DATA RECEIVED INTERRUPT REQUEST End Of Block or END OF BLOCK BTF=1 & TRA=1 ITE READY TO TRANSMIT INTERRUPT REQUEST or END OF BLOCK I2CSR1.EVF REOBP ITXM ITXP TEOBP Transmitting DMA End Of Block 9 |
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