ST92F124 datasheet(268/429 Pages) STMICROELECTRONICS

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I2C BUS INTERFACE

I2C BUS INTERFACE (Cont’d)

Figure 128. Transfer Sequencing

7-bit Slave receiver:

7-bit Slave transmitter:

7-bit Master receiver:

7-bit Master transmitter:

10-bit Slave receiver:

10-bit Slave transmitter:

10-bit Master transmitter

10-bit Master receiver:

Legend:

S=Start, Sr = Repeated Start, P=Stop, A=Acknowledge, NA=Non-acknowledge,

EVx=Event (with interrupt if ITE=1)

EV1: EVF=1, ADSL=1, cleared by reading SR1 register.

EV2: EVF=1, BTF=1, cleared by reading SR1 register followed by reading DR register or when DMA

is complete.

EV3: EVF=1, BTF=1, cleared by reading SR1 register followed by writing DR register or when DMA

is complete.

EV3-1: EVF=1, AF=1, BTF=1; AF is cleared by reading SR1 register, BTF is cleared by releasing the

lines (STOP=1, STOP=0) or writing DR register (for example DR=FFh). Note: If lines are released by

STOP=1, STOP=0 the subsequent EV4 is not seen.

EV4: EVF=1, STOPF=1, cleared by reading SR2 register.

S Address

Data1

Data2

.....

DataN

EV1

EV2

EV4

S Address

Data1

Data2

.....

DataN

EV1 EV3

EV3

EV3-1

EV4

Address

Data1

Data2

.....

DataN

EV5

EV6

EV7

Address

Data1

Data2

.....

DataN

EV5

EV6 EV8

EV8

S Header

Address

Data1

.....

DataN

EV1

EV2

EV4

Sr Header A

Data1

....

DataN

EV1 EV3

EV3

EV3-1

EV4

Header

Address

Data1

.....

DataN

EV5

EV9

EV6 EV8

EV8

Header

Data1

.....

DataN

EV5

EV6

EV7

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