ST92F124 datasheet(271/429 Pages) STMICROELECTRONICS

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I2C BUS INTERFACE

I2C BUS INTERFACE (Cont’d)

Note: Until the pending bit is reset (while the cor-

responding mask bit is set), the peripheral proc-

esses an interrupt request. So, if at the end of an

interrupt routine the pending bit is not reset, anoth-

er interrupt request is performed.

Note: Before the end of the transmission and re-

ception interrupt routines, the I2CSR1.BTF flag bit

should be checked, to acknowledge any interrupt

requests that occurred during the interrupt routine

and to avoid masking subsequent interrupt re-

quests.

Note: The “Error” event interrupt pending bit

(I2CISR.IERRP) is forced high when the error

event flags are set (ADD10, ADSL and SB flags of

the I2CSR1 register; SCLF, ADDTX, AF, STOPF,

ARLO and BERR flags of the I2CSR2 register).

Moreover the Transmitting End Of Block interrupt

has the same priority as the “Peripheral Ready to

Transmit” interrupt and the Receiving End Of

Block interrupt has the same priority as the “Data

received” interrupt.

10.8.6 DMA Features

The peripheral can use the ST9+ on-chip Direct

Memory Access (DMA) channels to provide high-

speed data transaction between the peripheral

and contiguous locations of Register File, and

Memory. The transactions can occur from and to-

ward the peripheral. The maximum number of

transactions that each DMA channel can perform

is 222 if the register file is selected or 65536 if

memory is selected. The control of the DMA fea-

tures is performed using registers placed in the pe-

ripheral

page

(I2CISR,

I2CIMR,

I2CRDAP, I2CRDC, I2CTDAP, I2CTDC).

Each DMA transfer consists of three operations:

– A load from/to the peripheral data register

(I2CDR) to/from a location of Register File/Mem-

ory addressed through the DMA Address Regis-

ter (or Register pair)

– A post-increment of the DMA Address Register

(or Register pair)

– A post-decrement of the DMA transaction coun-

ter, which contains the number of transactions

that have still to be performed.

The priority level of the DMA features of the I2C

interface with respect to the other peripherals and

the CPU is the same as programmed in the

I2CISR register for the interrupt sources. In the in-

ternal priority level order of the peripheral, the “Er-

ror” interrupt sources have higher priority, followed

by DMA, “Data received” and “Receiving End Of

Block” interrupts, “Peripheral Ready to Transmit”

and “Transmitting End Of Block”.

Refer to the Interrupt and DMA chapters for details

on the priority levels.

The DMA features are enabled by setting the cor-

responding enabling bits (RXDM, TXDM) in the

I2CIMR register. It is possible to select also the di-

rection of the DMA transactions.

Once the DMA transfer is completed (the transac-

tion counter reaches 0 value), an interrupt request

to the CPU is generated. This kind of interrupt is

called “End Of Block”. The peripheral sends two

different “End Of Block” interrupts depending on

the direction of the DMA (Receiving End Of Block -

Transmitting End Of Block). These interrupt

sources have dedicated interrupt pending bits in

the I2CIMR register (REOBP, TEOBP) and they

are mapped on the same interrupt vectors as re-

spectively “Data Received” and “Peripheral Ready

to Transmit” interrupt sources. The same corre-

spondence exists about the internal priority be-

tween interrupts.

Note: The I2CCR.ITE bit has no effect on the End

Of Block interrupts.

Moreover, the I2CSR1.EVF flag is not set by the

End Of Block interrupts.

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