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PCF5083H/5V2/F3 数据表(PDF) 118 Page - NXP Semiconductors |
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PCF5083H/5V2/F3 数据表(HTML) 118 Page - NXP Semiconductors |
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118 / 136 page  1996 Oct 29 118 Philips Semiconductors Objective specification GSM signal processing IC PCF5083 Host Interface timing (see Figs 29 and 30) 1 HR/W setup time to HCEN LOW 5 −− ns 2 HA0 to HA6 setup time to HCEN LOW 5 −− ns 3a HD0 to HD7 setup time (HCEN_T) t13 −− ns 3b HD0 to HD7 setup time (HCEN_D) 10 −− ns 4 HD0 to HD7 hold time after HCEN HIGH 10 −− ns 5 HR/W hold time after HCEN HIGH 5 −− ns 6 HA0 to HA6 hold time after HCEN HIGH 10 −− ns 7a HCEN pulse width (HCEN_T) 3t13 −− ns 7b HCEN pulse width (HCEN_D) 2tdclkout +20 −− ns 8(9) DTACK LOW delay time, DSP write cycle − 30 − ns 9 DTACK HIGH delay time, DSP read cycle; note 3 − 40 − ns 10(10) DTACK LOW delay time, DSP read cycle − 30 − ns 11 DTACK LOW to data valid; note 11 − 35 50 ns 12 DTACK HIGH delay time, DSP read cycle; note 3 − 40 − ns 13a HD0 to HD7 valid after HCEN LOW (HCEN_T) −− 3t13 ns 13b HD0 to HD7 valid after HCEN LOW (HCEN_T) −− 45 ns 14 HD0 to HD7 3-state after HCEN HIGH −− 30 ns RF Device Control Bus timing - Mode 0 (see Fig.31; note 12) 1 RFEN1 to RFEN4 setup time to RFCLK LOW − 4t13 − ns 2 RFEN1 to RFEN4 hold time after RFCLK HIGH − 2t13 − ns 3 RFCLK HIGH time − 6t13 − ns 4 RFCLK LOW time − 6t13 − ns 5 RFDO setup time to RFCLK HIGH − 10t13 − ns 6 RFDO hold time after RFCLK HIGH − 2t13 − ns 7(7) RFDI setup time to RFCLK HIGH 70 −− ns RF Device Control Bus timing - Mode 1 (see Fig.32; note 12) 1 RFEN1 to RFEN4 setup time to RFCLK HIGH − 4t13 − ns 2 RFEN1 to RFEN4 hold time after RFCLK LOW − 2t13 − ns 3 RFCLK LOW time − 6t13 − ns 4 RFCLK HIGH time − 6t13 − ns 5 RFDO setup time to RFCLK HIGH − 4t13 − ns 6 RFDO hold time after RFCLK LOW − 2t13 − ns 7(7) RFDI setup time to RFCLK LOW 70 −− ns NO PARAMETER MIN. TYP. MAX. UNIT |
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