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PCF5083H/5V2/F3 数据表(PDF) 119 Page - NXP Semiconductors

部件名 PCF5083H/5V2/F3
功能描述  GSM signal processing IC
PDF  136 Pages
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制造商  PHILIPS [NXP Semiconductors]
网页  http://www.nxp.com
标志 PHILIPS - NXP Semiconductors

PCF5083H/5V2/F3 数据表(HTML) 119 Page - NXP Semiconductors

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1996 Oct 29
119
Philips Semiconductors
Objective specification
GSM signal processing IC
PCF5083
RF Device Control Bus timing - Mode 2 (see Fig.33; note 12)
1
RFEN1 to RFEN4 setup time to RFCLK HIGH
−
4t13
−
ns
2
RFEN1 to RFEN4 hold time after RFCLK LOW
−
14t13
−
ns
3
RFCLK LOW time
−
6t13
−
ns
4
RFCLK HIGH time
−
6t13
−
ns
5
RFDO setup time to RFCLK HIGH
−
4t13
−
ns
6
RFDO hold time after RFCLK LOW
−
2t13
−
ns
7(7)
RFDI setup time to RFCLK LOW
70
−−
ns
8
RFE setup time to RFEN1 to RFEN4 LOW
−
6t13
−
ns
Baseband Interface timing (DSP Core X_Port) (see Fig.34)
1
SIXEN setup to SIXCLK HIGH
5
−−
ns
2
SIXD setup to SIXCLK HIGH
5
−−
ns
3
SIXD hold time after SIXCLK HIGH
10
−−
ns
4
SIXEN hold time after SIXCLK HIGH
10
−−
ns
5
SIXCLK frequency
−
13
−
MHz
6
SIXCLK LOW time
20
−−
ns
7
SIXCLK HIGH time
20
−−
ns
8
SOXEN setup time to SOXCLK LOW
20
−−
ns
10
SOXD hold time after SOXCLK LOW
−−
40
ns
11
SOXEN hold time after SOXCLK LOW
10
−−
ns
12
SOXD 3-state after SOXEN HIGH
−−
20
ns
13
SOXCLK frequency
−
0.27
13
MHz
14
SOXCLK LOW time
20
1800
−
ns
15
SOXCLK HIGH time
20
1800
−
ns
IOM -2 Interface timing (see Figs 35 and 36)
1(7)
DD hold time after DCL HIGH
−30
−
30
ns
2a(13)
DCL cycle time
−
8.5t13
−
ns
2b(13)
DCL cycle time
−
8t13
−
ns
2c(13)
DCL frequency
−
4.096
−
MHz
3(7)
FSC hold time after DCL HIGH
−30
−
30
ns
4(7)
DU setup time to DCL LOW
50
−−
ns
5(7)
DU hold time after DCL LOW
50
−−
ns
6(13)(7)
DCL HIGH time
75
−−
ns
7(13)(7)
DCL LOW time
75
−−
ns
NO
PARAMETER
MIN.
TYP.
MAX.
UNIT



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