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S12SCIV2/D 数据表(PDF) 116 Page - Freescale Semiconductor, Inc

部件名 S12SCIV2/D
功能描述  Device User Guide V01.18
PDF  130 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

S12SCIV2/D 数据表(HTML) 116 Page - Freescale Semiconductor, Inc

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MC9S12H256 Device User Guide — V01.18
Figure A-6 SPI Master Timing (CPHA =1)
Table A-17 SPI Master Mode Timing Characteristics1
NOTES:
1. The numbers 7, 8 in the column labeled “Num” are missing. This has been done on purpose to be consistent between the
Master and the Slave timing shown in Table A-18.
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs
Num C
Rating
Symbol
Min
Typ
Max
Unit
1
P Operating Frequency
fop
DC
1
/4
fbus
1P SCK Period tsck = 1./fop
tsck
4
2048
tbus
2
D Enable Lead Time
tlead
1
/2—
tsck
3
D Enable Lag Time
tlag
1
/2
tsck
4
D Clock (SCK) High or Low Time
twsck
tbus − 30
1024 tbus
ns
5
D Data Setup Time (Inputs)
tsu
25
ns
6
D Data Hold Time (Inputs)
thi
0ns
9
D Data Valid (after SCK Edge)
tv
25
ns
10
D Data Hold Time (Outputs)
tho
0ns
11
D Rise Time Inputs and Outputs
tr
25
ns
12
D Fall Time Inputs and Outputs
tf
25
ns
SCK
(OUTPUT)
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
1
5
6
MSB IN2
BIT 6 . . . 1
LSB IN
MASTER MSB OUT2
MASTER LSB OUT
BIT 6 . . . 1
4
4
9
11
12
10
PORT DATA
(CPOL
= 0)
(CPOL
= 1)
PORT DATA
SS1
(OUTPUT)
2
12
11
3
1. If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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