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S12SCIV2/D 数据表(PDF) 115 Page - Freescale Semiconductor, Inc

部件名 S12SCIV2/D
功能描述  Device User Guide V01.18
PDF  130 Pages
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制造商  FREESCALE [Freescale Semiconductor, Inc]
网页  http://www.freescale.com
标志 FREESCALE - Freescale Semiconductor, Inc

S12SCIV2/D 数据表(HTML) 115 Page - Freescale Semiconductor, Inc

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MC9S12H256 Device User Guide — V01.18
A.6 SPI
A.6.1 Master Mode
Figure A-5 and Figure A-6 illustrate the master mode timing. Timing values are shown in Table A-17.
Figure A-5 SPI Master Timing (CPHA = 0)
SCK
(OUTPUT)
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
SS1
(OUTPUT)
1
9
5
6
MSB IN2
BIT 6 . . . 1
LSB IN
MSB OUT2
LSB OUT
BIT 6 . . . 1
10
4
4
2
9
(CPOL
= 0)
(CPOL
= 1)
3
11
12
1. If configured as output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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