ADIN1100BCPZ-R7 datasheet(39/80 Pages) AD

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Data Sheet

ADIN1100

MDIO INTERFACE

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Rev. B | 39 of 80

CLAUSE 45

The clause 45 registers are made up of four device address

groupings (see Table 33) based on the MDIO manageable device

(MMD). Within each device address space, IEEE standard registers

are located in register addresses between 0x0000 and 0x7FFF and

vendor specific registers are located in register addresses from

0x8000 to 0xFFFF.

This setup allows access to up to 32 PHYs consisting of up to 32

MMDs through a single MDIO interface.

The IEEE Clause 45 MMD register access format is shown in Table

34 and Table 35.

Clause 45 operations differ from Clause 22 operations where a

single frame specifies the register address and data to read or

write. In Clause 45, a first frame is sent to specify the device

address and register address to access. A second frame is then

sent to perform the read or write operation on the selected device

address and register specified in the first frame.

Table 33. Register Groupings

Device Address

MMD Name

0x01

PMA and physical medium dependent (PMD)

0x03

PCS

0x07

Autonegotiation

0x1E

Vendor Specific 1

0x1F

Vendor Specific 2

Table 34. Clause 45 Frame Format

MSB

LSB

D31 to D30

D29 to D28

D27 to D23

D22 to D18

D17 to D16

D15 to D0

PHYADR

DEVAD

Address/data

Table 35. Clause 45 Input Register Decode

Bit

Description

2-bit start of frame (00 for Clause 45)

2-bit operation code

00: address

01: write

11: read

10: read + address

PHYADR

5-bit PHY address

DEVAD

5-bit device address

2-bit turn around field used to avoid contention during a read transition, 2-bit time spacing between register address field and data field

Address/Data

16-bit register address/data

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