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ADIN1100BCPZ-R7 数据表(PDF) 60 Page - Analog Devices

部件名 ADIN1100BCPZ-R7
功能描述  Robust, Industrial, Low Power 10BASE-T1L PHY
PDF  80 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADIN1100BCPZ-R7 数据表(HTML) 60 Page - Analog Devices

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Data Sheet
ADIN1100
REGISTER SUMMARY
analog.com
Rev. B | 60 of 80
Table 83. Bit Descriptions for AN_B10_ADV_ABILITY (Continued)
Bits
Bit Name
Description
Reset
Access
12
AN_B10_ADV_B10L_TX_LVL_HI_REQ
10BASE-T1L High Level Transmit Operating Mode Request. This is a
duplicate of the AN_ADV_B10L_TX_LVL_HI_REQ bit.
Pin dependent
R/W
[11:0]
RESERVED
Reserved.
0x0
R
10BASE-T1 Autonegotiation Status Register
Device Address: 0x07; Register Address: 0x020F, Reset: 0x0000, Name: AN_B10_LP_ADV_ABILITY
This address corresponds to the 10BASE-T1 autonegotiation status register specified in Clause 45.2.7.26 of Standard 802.3cg.
Table 84. Bit Descriptions for AN_B10_LP_ADV_ABILITY
Bits
Bit Name
Description
Reset
Access
15
AN_B10_LP_ADV_B10L
10BASE-T1L Ability. This is a duplicate of the AN_LP_ADV_B10L bit.
0x0
R
14
AN_B10_LP_ADV_B10L_EEE
10BASE-T1L EEE Ability. This is a duplicate of the AN_LP_ADV_B10L_EEE bit. 0x0
R
13
AN_B10_LP_ADV_B10L_TX_LVL_HI_ABL
10BASE-T1L High Level Transmit Operating Mode Ability. This is a duplicate of
the AN_LP_ADV_B10L_TX_LVL_HI_ABL bit.
0x0
R
12
AN_B10_LP_ADV_B10L_TX_LVL_HI_REQ
10BASE-T1L High Level Transmit Operating Mode Request. This is a duplicate
of the AN_LP_ADV_B10L_TX_LVL_HI_REQ bit.
0x0
R
[11:8]
RESERVED
Reserved.
0x0
R
7
AN_B10_LP_ADV_B10S_FD
Link Partner 10BASE-T1S Full Duplex Ability. This is a duplicate of the
AN_LP_ADV_B10S_FD bit.
0x0
R
6
AN_B10_LP_ADV_B10S_HD
Link Partner 10BASE-T1S Half-Duplex Ability. This is a duplicate of the
AN_LP_ADV_B10S_HD bit.
0x0
R
[5:0]
RESERVED
Reserved.
0x0
R
Autonegotiation Forced Mode Enable Register
Device Address: 0x07; Register Address: 0x8000, Reset: 0x0000, Name: AN_FRC_MODE_EN
The effect of this register is superseded by the AN_EN bit, which enables the autonegotiation process. If autonegotiation is disabled (AN_EN =
0) and AN_FRC_MODE_EN = 1, forced mode is enabled.
Table 85. Bit Descriptions for AN_FRC_MODE_EN
Bits
Bit Name
Description
Reset
Access
[15:1]
RESERVED
Reserved.
0x0
R
0
AN_FRC_MODE_EN
Autonegotiation Forced Mode. Enables forced mode functionality.
0x0
R/W
Extra Autonegotiation Status Register
Device Address: 0x07; Register Address: 0x8001, Reset: 0x0000, Name: AN_STATUS_EXTRA
This register is provided in addition to AN_STATUS.
Table 86. Bit Descriptions for AN_STATUS_EXTRA
Bits
Bit Name
Description
Reset
Access
[15:11]
RESERVED
Reserved.
0x0
R
10
AN_LP_NP_RX
Next Page Request Received from Link Partner.
0x0
R LH
9
AN_INC_LINK
Incompatible Link Indication. This corresponds to the incompatible link state of IEEE Standard
802.3 Subclause 98.5.1. Its value is set by the priority resolution function run on entering the
autonegotiation good check state.
0x0
R



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